A High Precision Low Distortion Current Squarer/Divider Circuit Based on FGMOS Translinear Principle

SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT) detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when PVT variations are detected. The PVT detector is based in the propagation delay of digital buffers. When an increase in the propagation delay is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and characterized in a TSMC 28 nm bulk CMOS technology.

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

In this paper, a PVT (process, voltage and temperature)-insensitive Ka-Band Class-D VCO with average current control in 65 nm CMOS process is presented. The proposed VCO is based on a Class-D VCO architecture to achieve good noise performance and low power consumption. Different from the traditional structure, a tail current source is added to control the average operation current of the VCO. This structure can achieve a stable VCO performance against PVT variations. And the output phase noise of the VCO is immune to the noise and ripples on the external power supply owing to the power supply rejection characteristic of the current source. Moreover, a typical internal power supply circuit is introduced and a minor improvement is addressed to realize the current source without deteriorating the total VCO phase noise. Quantitative analysis and simulation indicate that the proposed structure removes the strict requirements to the power supply circuits comparing to the traditional scheme. The experimental results show that at the frequency of 34.5 GHz, the phase noise of the proposed VCO is - 98 dBc/Hz at 1 MHz offset with the power supply circuit, the core power is 1.7 mW, and the core area is 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability. In this paper, we show that compared with the static random variation, RTN amplitude of a particular device is not constant across supply voltages and temperatures. A device may show large RTN amplitude at one operating condition and small amplitude at another operating condition. As a result, RTN amplitude distribution becomes uncorrelated across a wide range of voltage and temperature. The emergence of uncorrelated distribution causes significant degradation of worst-case values. Analysis results based on variability models from a 65 nm silicon-on-insulator process show that uncorrelated RTN degrades the worst-case threshold voltage value significantly compared with that where RTN is not considered. Delay variation analysis shows that consideration of RTN in the statistical analysis have little impact at high supply voltage. However, at low voltage operation, RTN can degrade the worst-case value by more than 5 %.

Although Artificial Neural Networks (ANNs) are inspired by biological neural systems, most of ANNs today are implemented with digital circuitry and use binary values in computation. In recent years, analog-based neuromorphic system has gained lots of attention as it provides a natural interface for brain-machine interaction. In this paper, we present analog designs of a complete neuron system, where the Multiply-Accumulate (MAC) and Rectified Linear Unit (ReLU) functions are all implemented in analog circuits. The design uses SMIC 55nm standard LP CMOS process node and operates at low supply voltage (1.2 V). The simulation results in SPECTRE demonstrate that the MAC's linear error is no more than 0.5% and total harmonic distortion (THD) is less than 1.6% when the inputs vary from peak (-10 µA) to peak (10 µA) at 10 MHz, the -3dB bandwidth is 288 MHz, the maximum power consumption is 540 µW and the static power consumption is 493 µW under 100MHz input signal frequency. More specifically, our design is resilient to the fluctuation of power supply, which helps to achieve high precision of computation.

This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at 32 nm level that utilizes different input voltages for verifying voltage follower performance. The fully differential architecture suppresses the common mode interference. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.

In this paper, we proposed a Ring Time-to-Digital Converter (RTDC)-based Capacitance-to-Digital Converter (CDC) that is insensitive to PVT variation. The proposed CDC embeds a Capacitance-to-Time Converter (C2T) with high linearity, leveraging a parasitic elimination technique to counteract environment changes. Thanks to the ring structure of RTDC, the presented CDC has theoretically infinite detection range. However, RTDC suffers from the process, voltage and temperature (PVT) variation, compromising its dynamic range. This paper proposed a new architecture that matches the current sources of the front-end and delay cells in the RTDC. Therefore, the front-end and RTDC have the same PVT response, leading to an inherent-PVT-stabilized feature. The proposed CDC was implemented in a 40-nm LP CMOS process. Simulation results show that it achieves 0.55fF resolution under 10pF parasitic capacitance and it covers 3.75-64pF capacitance detection range, with a 0.56pJ/conversion-step figure of merit and a maximum 20us conversion time.

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

In this paper, a CMOS ultra-low-power, high-speed four-quadrant current multiplier/divider circuit is presented. Based on square-difference approach, the proposed circuit is using a new current squarer with MOS transistors operating in weak inversion region. The translinear loops are the basic building blocks in realization of the current-mode two-quadrant squarer and four-quadrant multiplier/divider circuits. The proposed designs have been simulated using HSPICE in 0.18 $$\upmu \hbox {m}$$ TSMC CMOS (level-49 parameter) process. Post-layout simulation results with 0.8 V power supply show the total power dissipation of 770 nW, the total harmonic distortion of 0.67% (at 100 kHz), the maximum linearity error of 2%, and the − 3 dB bandwidth of 34.1 MHz. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage, and temperature) variations.

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 μm CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a −54 dB total harmonic distortion (THD) and more than 1 GHz − 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass gm-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.

Process, voltage and temperature (PVT) variations in emerging ultra-deep submicron (UDSM) technology nodes critically affect device performances and limit further scaling of such devices based on Moore's law. This paper proposes CNFET-based design of robust Schmitt trigger circuits, which outperform their CMOS counterparts in terms of mean values as well as variabilities of all considered design metrics. Popular Schmitt trigger designs are investigated and a comparative analysis is carried out based on Monte Carlo simulations in an HSPICE environment, using the 16-nm CMOS Predictive Technology Model (PTM), to choose the designs with best performance in terms of variability of design metrics such as power, power-delay product (PDP) and hysteresis width. These are then re-designed with corresponding optimized devices using the experimentally validated Stanford University CNFET model. The proposed CNFET-based circuits provide a 9.9×, 11.8× and 22× improvement in power, PDP and hysteresis width variability respectively, while also providing better noise immunity through increased hysteresis widths, thus demonstrating their superiority to CMOS circuits in all respects at highly scaled technology nodes.

PVT-compensated low voltage LNA based on variable current source for low power applications

This paper presents a spread-spectrum clock generator (SSCG) based on voltage-controlled oscillator (VCO) direct modulation. An auxiliary frequency-locked loop has been employed to guarantee a stable and accurate spread ratio under the variations of process, voltage and temperature (PVT). Besides, the spread ratio can be programmed via different counting value in the auxiliary loop. Implemented in UMC 0.18-μm CMOS technology, the SSCG achieves a 9.97 dB reduction in the peak power spectrum with 0.5% spreading at 31.56 kHz modulation frequency. The die area of the SSCG is 0.42×0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .