Automated AC (timing) characterization for digital circuit testing

Ensuring correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints. Static Timing Analysis is the procedure performed to calculate the setup and hold time of any digital circuit and to check for any setup and hold time violations. This paper presents the methodology to perform setup and hold time analysis for different designs of Master Slave D Flip-Flop using 18 nm FinFET technology. FinFET technology was chosen since it is the prevalent technology in the industry. Implementation of D Flip-Flop design, suitable test circuit and timing analysis is performed on the Cadence virtuoso analog design environment tool. Using appropriate excitations, parametric analysis is carried out to obtain the setup and hold time values for various designs of D Flip-Flop including the proposed design. From the results, it was observed that the setup time and hold time varied with different clock edge rates. For the edge rates of 0.01, 0.05, and 0.1 ns, it was observed that the proposed design gave setup times of 54.9, 61.2, and 69.8 ps and hold times of −30.7, −43.6 and, −48.8 ps, respectively. On comparing all the results, it was observed that the GDI MUX and pass transistor-based designs gave a good trade-off between transistor count, setup time and hold time. For the proposed design, although the setup times were slightly on the higher side, the hold time values were more negative which is always preferred.

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 p m TSMC process (CM018) to test chip I/O speeds, specijkally, the setup and hold times of I10 registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also employs an eight-stage shift averaging voltagecontrolled delay line (VCDL) to improve the matching between delay stages and thus to equalize the delay of each individual stage. The locking failure or false locking problems are alleviated by using a start-control circuit. setup and hold times are two of the key metrics to evaluate the register or buffer's AC electrical characteristics. Therefore, it is important to test the specifications on setup and hold times. These tests will fail if the delays from the data inputs to the registers and from the clock input to the registers differ such that the data is not valid before (setup time) and after (hold time) the clock is asserted. This may happen due to delays in long buffered interconnect lines and in the clock tree. In order to satisfy the timing requirements, the delay in the clock tree must be larger than the delay for the data input by the setup time requirement, but not so large as to violate the hold time requirement.

A novel solution to the problem of correcting leaded semiconductor packages damaged during test and handling is presented. The elimination of the high costs of reworking and maintaining lot integrity is accomplished by integrating a highly programmable lead conditioning system with the traditional lead inspection system. The equipment accommodates gull and J lead forms via a quick change lead conditioning tool. Devices ranging from 10 mm to 40 mm, square, rectangular, two or four sided can be effectively conditioned with no increase in setup time or decrease in overall throughput. The effectiveness or device recovery rate of such a system is documented with data from semiconductor manufacturing and printed board assembly environments. While previous methods relied on huge amounts of hand labor and very expensive hard tooling, the programmable conditioner allows a high product mix within the setup and changeover time of the inspection equipment. Data demonstrating the effectiveness and versatility of a `one-lead-at-a-time' conditioner is presented. Although the throughput is less than for inspection alone, the total cycle time and throughput are actually higher than for process configurations which separate inspection and conditioning. Conventional processing flows impose severe cycle time delays, hand labor costs and re-inspections that are eliminated in the integrated system. The major factors of determining the payback and justification for an integrated system are also discussed. The economic factors discussed include direct labor, capital cost, tooling cost and cycle time. Systems justified to date have done so on the basis of a single factor, the value of the recovered units. Intangible factors are also identified and discussed.

A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT) detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when PVT variations are detected. The PVT detector is based in the propagation delay of digital buffers. When an increase in the propagation delay is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and characterized in a TSMC 28 nm bulk CMOS technology.

In this paper we report the characterizations results of serial peripheral interface (SPI) timing parameters for optical mouse sensor. SPI is an interface that facilitates the transfer of synchronous serial data. It supports two-way communication between mouse sensor and microcontroller. The test setups were used consist of digital oscilloscope, power supply, mouse sensor, test board and personal computer. The SPI timing parameters that were evaluated are read- address data delay, the timing between read and subsequent commands, rise and fall time, hold time, setup time, NCS to SCLK active, SCLK to NCS inactive (read operation) and SCLK to NCS inactive (write operation). The timing parameters results were within the limit as specified in product datasheet.

Abstract. Due to the increasing importance of EMC problems through the last years there is a great interest in measurement devices such as GTEM-cells (Giga(Hz)- TEM cells). They promise to allow compact and low-cost emission- as well as susceptibility tests up to very high frequencies. Expensive measurement procedures in open-area test sites or within semi-anechoic chambers would become obsolete in many cases. To estimate the quality and reliability of GTEM-cell measurements it is necessary to have detailed knowledge about the processes within the cell and, in particular, about the interactions between the cell and the DUT (device under test). Due to the high frequency and the cell’s dimensions a purely numerical simulation while using standard techniques such as Finite Element Method, Method of Moments (MoM) or the Finite-Differ-Time-Domain (FDTD) method is inefficient and unnecessary since the GTEM-cell is a mostly empty homogeneous TEM-waveguide. Analytical models allow only the investigation of empty cells. As will be outlined in the following, a suitable way to reduce the numerical complexity of the general problem is the use of a hybrid method, such as the combination of a modal analysis with the MoM.

Verilog-1995 added the ability to specify a negative setup or hold time (but not both) with the $ setuphold timing check. However, the Verilog-1995 standard was somewhat ambiguous on how a negative setup or hold time should be processed by simulators. The Verilog-1995 standard for $setuphold is:

A review is presented of the contactor in testing of high-speed ICs. The contactor, which establishes temporary connections to the leads of the device under test (DUT), must not impair the electrical performance of the DUT. In addition, it must have mechanical and thermal characteristics suitable for automatic environmental handling. The author concludes that although the ideal or perfect test contactor does not yet exist, contactor design is keeping pace with advances in the integrated-circuit industry. >

The aim of this master thesis is to develop a high-bandwidth current sensor for a nominal design current of 100 A and a nominal design bandwidth of 100 MHz. After an analysis which properties are important to develop a current sensor, a requirement list was stated. Several current sensing methods were described and their qualification for the stated requirements were evaluated. With the resulting sensing concept, consisting out of Rogowski coils and magneto resistors, a system design was elaborated. One requirement was to develop a current sensor which needs less effort in series production than a regular Rogowski coil. Therefore, a planar Rogowski coil was proposed for this sensor development. Furthermore, a magnetic field simulation was designed. Based on the results, a optimal placement simulation for both sensors was carried out. In the final design phase, the galvanic insulation requirements of 4.8 kV based on the corresponding standards were investigated and implemented. The test equipment used in this thesis was designed and build in-house at IPE (KIT-ADL). Commercial solutions did not offer the suggested requirements for generating a double pulse with the necessary rise time to characterize the current sensor’s bandwidth. The test equipment was able to apply pulses with a maximum current of 200 A and a rise time of 1 ns to the device under test. The prototype is able to sense a current up to ±100 A with a bandwidth of 20 MHz.

Finite-point method for efficient timing characterization of sequential elements

On the system with gated clock, NBTI causes the unbalanced degradation in the threshold voltage of PMOSFETs. In this paper, we clarify the impact of NBTI degradation on timing characteristics such as setup time, hold time and clock skew. We demonstrate that the maximum operating frequency regarding setup time violation becomes worse, hold time constraint becomes better, and clock skew after a gated clock cell operates better with stopped time.

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

The key player in the multi-clock domain system is the synchronizer. This synchronizer suffers from the effect of metastability and results in the failure of the circuit. Prevention of the synchronizer from the metastability is feasible. Metastable state occurs whenever there is a violation of setup and hold time i.e., uncontrolled and unpredictable change in data within setup and hold time window. In this paper, we proposed a new architecture of the synchronizer. It detects any transitions in data signal within metastability window. The closed loop gains of the cross-coupled inverter are controlled by the external signal. This signal will ensure the correct state of the synchronizer. The additional part of the latch comes into action when this ambiguity occurs. The correctness of the circuit functionality is verified using HSPICE and Tanner EDA at the 32nm technology.

Latches and flip-flops are basic sequential logic devices. The operation of SR and D latches are presented. The application SR latch for eliminating contact bounces in mechanical switches is explained. The operation of D, T and JK flip-flops is explained. Flip-flops using Master-Slave latches are also explained. Set-up time and hold time are the timing requirements of flip-flops. The timing requirements of flip-flop are defined and the method of measuring them is presented.

The effect of aging has become an important reliability concern in modern CMOS technology. NBTI and PBTI are known to bring about an increase in threshold voltage of the PMOS and NMOS respectively. This paper studies the effect of NBTI and PBTI on different flip-flop circuits with key parameters such as setup time, hold time, clock to output delay and data to output delay. The results in a predictive 32 nm technology show an increase of 0.43 to 1.23 pico-seconds in data-to-output delay depending on the Flip-Flop type. Moreover, we propose a method to use dual threshold voltage assignment to mitigate the effect of transistor aging on pulse triggered Flip-Flops. Dual V th results show lower delay as well as 30% reduction in delay aging using the proposed dual threshold voltage method.