An Architecture Description Language for Embedded Hardware Platforms

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.

ABSTRACTStarch materials have been widely used in fields of flexible sensing and food 3D printing; rice starch (new source) needs in‐depth research for related applications. In this research, a mixing‐temperature controlling‐cold drying preparation scheme for rice starch gel with stable performance is proposed. In order to in‐depth analyze the rice starch internal structural–mechanical behavior, a developed texture analyzer with in situ observation is self‐established; the gel internal structure, mechanical behavior, and loading capacity are in‐depth analyzed. Effects of rice starch kind (indica, japonica, glutinous) and starch concentration are investigated on internal structure evolution and mechanical behavior. Experimental results show the starch gel is of crosslink network internal structure with pores. The starch dry gel compression force–displacement curve exhibits an S‐shaped relation. It can be divided into three stages: elastic deformation, micro‐cracking, and overall fracture, matching with rice dry gel internal structure evolution. Rice dry gel peak bearing force order is glutinous starch > indica starch > japonica starch, negatively correlated with internal network structure pore size. The dry gel internal pore size turns out to be small with increasing rice starch concentration. Based on rice starch dry gel mechanical and micro‐structure analysis, rice starch gels exhibit optimal structure for application.

The number of bus transactions in System-on-Chip (SoC) grows significantly in recent years. Because of different timing constraints for different applications, how to find a proper priority assignment for processing elements (PEs) of SoC becomes very challenging. In this paper, we first show that the priority assignment problem with one unique priority for each PE is NP-complete. When each bus transaction can have one unique priority, we propose an optimal priority assignment algorithm for a given workload. We then propose a priority assignment strategy based on Simulated Annealing (SA) for PEs, where bus arbitration is done in a priority-driven fashion. The objective is to minimize the number of priorities needed for each PE and to satisfy the timing constraints of applications. The experimental results show some encouraging results in priority assignment.

We have been investigating the efficiency of genetic algorithms (GA) for solving for a variety of real problems. During our investigations we have concluded that the large amount of computational time required to find GA based solutions on conventional computers is restrictive. We are therefore developing an innovative new computer architecture, suitable for the solution of large scale problems using GAs. In this paper we introduce the SIMD-GA (Single Instruction stream Multiple Data stream Genetic Algorithm), and discuss its hardware design and implementation. By taking advantage of the recent advances is HDLs (Hardware Description Language) and FPGAs (Field Programmable Gate Array) we have been able to quickly develop and prototype a PE (Processing Element) for a SIMD-GA. This approach allows us to build a cost-effective parallel processing architecture to overcome the problem of the computational time required for traditional sequential GA implementation.

Mixed‐signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face‐to‐face‐type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources. Copyright © 2008 John Wiley & Sons, Ltd.

Background/Objectives: The main objective of the paper is to implement a reconfigurable ALU that is a combination of a 32-bit floating point adder/subtractor and integer ALU. The integer ALU performs integer functions and logical operations such as addition, subtraction, shifting and comparison. Methods/Statistical analysis: In this paper, a 32-bit single precision format based on IEEE754 standard for the floating-point unit, with a 23-bit mantissa, 8-bit exponent and 1-bit sign value is considered. Findings: Verilog Hardware Description Language (HDL) is used and simulated by model sim simulator and then synthesized with Spartan3E FPGA. The functional unit uses 25% number of slices, 9% number of slice flip-flops, 18% of 4 input LUTs. From the timing report, the maximum frequency obtained is 81.614MHz. The maximum power obtained by the system is 82.46mW. Applications/Improvements: This can be used for data-parallel and computation intensive applications and in multimedia applications.

The goal of the paper is to present a novel approach for designing massively parallel architectures for image recognition systems. Massive parallel hardware produces high speed image recognition. Hardware architectures work much faster and are more effective for application specific processing than a software-based image recognition system. The concept of designing optimal image recognition systems with high speed, low complexity, good portability, and low cost has been present for a long time. The authors have considered the basic design factors, simple and regular design, concurrency and communication, and balancing computation with I/O. The technique presented provides a new method of designing an image recognition system by concentrating on modularity and massive parallelism. This is accomplished through the design of a processing element layer, local communicator layer, and network of new image layer. The processing element (PE) layer performs the basic recognition functions on individual pixels through logical operations. Both the local communicator and network of new image layers institute a mesh network topology, which has proven to be the fastest and most efficient. The local communicator layer has the most important function, it communicates with the other two layers, combines results from the PE layer, and houses the main control unit. All layers work simultaneously, or in other words, in a parallel fashion. The flow diagram of a CAD designer algorithm, based on this new design technique, is presented.

This paper presents a JAVA based framework for RTL modeling and simulation of digital hardware designs. After linking between object-oriented concepts and RTL models, the JAVA analogy to features found in a widely used hardware description language like Verilog is laid down. While focusing primarily on synchronous designs and cycle based simulation, the way to broaden this scope to event driven simulation is pointed out. Using a general object-oriented programming language for RTL modeling and simulation paves way for a more seamless software and hardware integration of a typical digital system.

VHDL as a hardware description language has some short-comings for system level modeling. Since previous researches [10] tried to extend this language for high level modeling, using Ada structures, and also it has derived some of its basic structures from Ada at first, we have decided to extend Ada to a form called SystemAda that can model hardware at transaction level modeling. Ada because of its intrinsic features like concurrency and object orientation can be a good candidate for a high level hardware modeling language. In our previous works we have proved that Ada can have a link to Register Transfer Level (RTL) and Transaction Level Modeling (TLM) modeling [3]. Here we have proofed the detailed characteristics of our TLM_FIFO channel -- just like the real TLM_FIFO -- and a way to TLM2.0 interfaces. Finally by simulation time comparison between SystemAda and SystemC TLM equivalent models we have proved that there is no simulation time penalty in SystemAda over SystemC.

7 - More Unix Philosophy: Ten Lesser Tenets

Chapter 1 describes the early work of von Neumann (1951) on cellular automata. This work was not accompanied by reductions to practice in hardware as it was impractical at that time to build machines having the millions of devices required. Only with the development of high-density integrated circuitry in the 1970s has this feat now been accomplished (Chapter 11). Therefore, during the 1950s cellular automata were emulated using the general-purpose computers which were available at that time. The work of Moore (1966) and Kirsch (1957) at the National Bureau of Standards, of Ulam (1962) at the Atomic Energy Commission, and Unger (1959) at Bell Telephone Laboratories are outstanding examples of this work. All of these workers simplified von Neumann’s 29-state processing element and concentrated their efforts on studying arrays of 2-state (binary) processing elements. In the 1960s a new trend began with the construction of the first cellular logic machines by one of the authors (Preston, 1961). These and other special-purpose machines emulated the cellular automaton by using a single high-speed processing element to operate sequentially on an array of binary data. With the introduction of the diff3 in the 1970s (Graham, and Norgren, 1980) cellular logic machines were manufactured having several processing elements. Then Sternberg (1981) introduced a pipelined cellular logic machine, called the Cytocomputer, having approximately 100 processing elements. The Cytocomputer was also the first cellular logic machine to include numerical (multi-state) processing elements in addition to binary processing elements, thus making the transition from high-speed special-purpose machines limited to bilevel data to a system which could manipulate multi-state data. This chapter concentrates on the evolution and architecture of the cellular logic machines which have been built over the past two decades, all of which handle bilevel data arrays. Machines of this kind are currently in wide use both for commercial and research purposes in image processing. Despite their limitation to bilevel data, they are also useful in graylevel image processing due to their ability to convert graylevel images to binary images by multiple thresholding and, after performing logical operations at these thresholds, to convert results to graylevel output by arithmetic summation (Chapter 2).

Due to the quick advancements in the personal communications systems and wireless communications, giving data security has turned into a more essential subject. This security idea turns into a more confounded subject when next-generation system requirements and constant calculation speed are considered in real-time. Hash functions are among the most essential cryptographic primitives and utilized as a part of the many fields of signature authentication and communication integrity. These functions are utilized to acquire a settled size unique fingerprint or hash value of an arbitrary length of message. In this paper, Secure Hash Algorithms (SHA) of types SHA-1, SHA-2 (SHA-224, SHA-256) and SHA-3 (BLAKE) are implemented on Field-Programmable Gate Array (FPGA) in a processor structure. The design is described and implemented using a hardware description language, namely VHSIC “Very High Speed Integrated Circuit” Hardware Description Language (VHDL). Since the logical operation of the hash types of (SHA-1, SHA-224, SHA-256 and SHA-3) are 32-bits, so a Superscalar Hash Microprocessor without Interlocked Pipelines (MIPS) processor are designed with only few instructions that were required in invoking the desired Hash algorithms, when the four types of hash algorithms executed sequentially using the designed processor, the total time required equal to approximately 342 us, with a throughput of 4.8 Mbps while the required to execute the same four hash algorithms using the designed four-way superscalar is reduced to 237 us with improved the throughput to 5.1 Mbps.

The book is devoted to the research and development of methods for combining computational structures for reconfigurable signature-based information protection tools for computer systems and networks in order to increase their efficiency. Network security tools based, among others, on such AI-based approaches as deep neural networking, despite the great progress shown in recent years, still suffer from nonzero recognition error probability. Even a low probability of such an error in a critical infrastructure can be disastrous. Therefore, signature-based recognition methods with their theoretically exact matching feature are still relevant when creating information security systems such as network intrusion detection systems, antivirus, anti-spam, and wormcontainment systems. The real time multi-pattern string matching task has been a major performance bottleneck in such systems. To speed up the recognition process, developers use a reconfigurable hardware platform based on FPGA devices. Such platform provides almost software flexibility and near-ASIC performance. The most important component of a signature-based information security system in terms of efficiency is the recognition module, in which the multipattern matching task is directly solved. It must not only check each byte of input data at speeds of tens and hundreds of gigabits/sec against hundreds of thousand or even millions patterns of signature database, but also change its structure every time a new signature appears or the operating conditions of the protected system change. As a result of the analysis of numerous examples of the development of reconfigurable information security systems, three most promising approaches to the construction of hardware circuits of recognition modules were identified, namely, content-addressable memory based on digital comparators, Bloom filter and Aho–Corasick finite automata. A method for fast quantification of components of recognition module and the entire system was proposed. The method makes it possible to exclude resource-intensive procedures for synthesizing digital circuits on FPGAs when building complex reconfigurable information security systems and their components. To improve the efficiency of the systems under study, structural-level combinational methods are proposed, which allow combining into single recognition device several matching schemes built on different approaches and their modifications, in such a way that their advantages are enhanced and disadvantages are eliminated. In order to achieve the maximum efficiency of combining methods, optimization methods are used. The methods of: parallel combining, sequential cascading and vertical junction have been formulated and investigated. The principle of multi-level combining of combining methods is also considered and researched. Algorithms for the implementation of the proposed combining methods have been developed. Software has been created that allows to conduct experiments with the developed methods and tools. Quantitative estimates are obtained for increasing the efficiency of constructing recognition modules as a result of using combination methods. The issue of optimization of reconfigurable devices presented in hardware description languages is considered. A modification of the method of affine transformations, which allows parallelizing such cycles that cannot be optimized by other methods, was presented. In order to facilitate the practical application of the developed methods and tools, a web service using high-performance computer technologies of grid and cloud computing was considered. The proposed methods to increase efficiency of matching procedure can also be used to solve important problems in other fields of science as data mining, analysis of DNA molecules, etc. Keywords: information security, signature, multi-pattern matching, FPGA, structural combining, efficiency, optimization, hardware description language.

Modern Systems-on-a-Chip (SoC) are constructed by composition of IP (Intellectual Property) Cores with the communication between these IP Cores being governed by well described interaction protocols. However, there is a disconnect between the machine readable specification of these protocols and the verification of their implementation in known hardware description languages. Although tools can be written to address such a separation of concerns, such tooling is often hand written and used to check hardware designs a posteriori. We have developed a dependent type-system and proof-of-concept modelling language to reason about the physical structure of hardware interfaces respective to user provided descriptions. Our type-system provides correct-by-construction guarantees that the interfaces on an IP Core will be well-typed if they adhere to a specified standard.