整合SDRAM控制器、主僕式矽智財、與SoC匯流排分析儀之系統晶片設計架構

Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Partial success has been achieved in deploying them. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of, design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. Another reason for the need to formalize is that, as designs become more complex, functional verification will have to be carried out using the divide and conquer approach.We discuss several approaches based on compositional verification. For these approaches to succeed, specifications of either, the individual modules, or individual IPs, if any are used, have to be stated formally. There exist several commercial offerings addressing the area of SoC functional verification. Most of these use some form of divide and conquer approach related to compositional verification. The basis of success of some of these tools lies in the fact that the specifications of the IP cores are in essence captured in some executable form, be they formal specification languages, or commonly used HDLs suitably modified for the purpose.This tutorial is structured to provide information on the state of the art in the area of functional verification. It will focus on existing methodologies, tools, and practical approaches based on universal simulation, emulation, formal verification, and semi-formal verification that can be employed to overcome the SoC verification problem. We discuss a number of real life verification projects, describing the various techniques used and the effectiveness of these techniques. We conclude the tutorial by presenting issues, which form the current focus for research.

In modern complex systems-on-chip (SoC), software as an integral part of the SoC is gaining more and more importance. With increasing SoC complexity, SoC designers are facing an increasing complexity in the system's architecture other than the HW issues alone. The intricacy of the software needed to run on such devices is increasing tremendously as well. The challenges regarding design flow, design automation and verification cannot be solved looking at the HW aspects of the design alone. There is a big need for SoC designers to understand both their classical - the HW - world, and the world of embedded software as well. Particular attention needs to be paid on questions like: how to deal with IP reuse that is composed of HW and SW; how does SW affect the design flow; how to enable portability across hardware platforms, different application domains, and so forth. This paper introduces embedded software for SoC and EDA designers, and tries to raise their awareness on software issues they are directly impacted by. However, both classical HW designers and embedded software designers have a lot to teach each other, therefore mutual understanding is crucial for solving the SoC design challenges. In the last part of this paper, the concept of hardware dependent software (HdS) is introduced, and how HdS can help to solve some of the issues mentioned before.

Logic design has become very complex in term of logic functionality. System-on-chip (SOC) designs are an integration of multiple modules and cores. In many cases, SOC integration is a result of integrating a few chips together. Each piece (module or core) must be verified separately (stand alone) prior to chip level verification. Standalone logic verification of the design is one of the most important steps in the overall design effort. Following the increase of the amount of functionality at each module, the logic verification effort has become a very resource-consuming task. Two logic verification methods are commonly used when verifying a SOC, simulation based verification and formal based verification. The two methods are explored and compared with respect to the time required for setup and running the environment, ease of debugging the reported failures, power, coverage and confidence level. Our main goal is to establish criteria for optimal use of simulation based verification and formal based verification and implement both methods on a block for a PCMCIA interface card. We have derived important conclusions concerning the matching of these methods for the verification of blocks of a similar type.

Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. To be able to exploit the large performance vs. area search space of such modern FPGA-based SoCs, system architects must have the appropriate performance analysis tools to evaluate-preferably at runtime-the computational requirements and the data flow of such a system to determine potential performance bottlenecks when running realistic workloads. In this paper we introduce SoCLog, a framework that automatically enhances the platform architecture with additional hardware components used to generate activity logs when the base SoC architecture executes an application. This real-time information can be analyzed by the system designer to expose performance bottlenecks not only on aggregate, but also at clock cycle granularity thus revealing potential design inefficiencies when there is burst of activity in the system. We evaluate our framework with a number of SoC designs to show that such a logging information can be valuable for the design of a complex SoC in a modern FPGA with minimal area overhead.

Validation of an System-on-Chip (SoC) design with networking capability needs global simulation of the whole system including the network as well as the SoC design itself. Especially, it is needed to validate the interoperability of SoCs from different vendors. In this paper, we propose a simulation environment and simulation techniques for efficient validation of such SoC designs and apply them to networked Bluetooth SoC designs. The environment enables two types of simulation. One is modular enough to include the simulation of other vendors' Bluetooth devices and the other is optimized to achieve fast simulation in developing in-house Bluetooth devices. Especially, the former is scalable in that it keeps the constant simulation runtime despite the increase of the number of Bluetooth devices. Since multiple simulators are involved, the global simulation is still slow. Thus, the simulation efforts need to be minimized to shorten the design cycle. We present two simulation techniques, a concept called grouped message for reduction in simulation runtime and a system debug scenario called fix---modify---restart for reduction in the number of simulation runs. The former is to reduce inter-process communication overhead between simulators in the global simulation. The latter is to reduce repeated simulation runs in the conventional design cycle. Experimental results show the scalability of the presented simulation environment, reduction in simulation efforts by two simulation techniques.

In testing systems with distributed interfaces/ports, we may place a separate tester at each port. It is known that this approach can introduce <it>controllability problems</it> which have received much attention in testing from finite state machines. Message sequence charts (MSCs) form an alternative, commonly used, language for modelling distributed systems. However, controllability problems in testing from MSCs have not been thoroughly investigated. In this paper, controllability problems in MSC test cases are analysed with three notions of observability: local, tester and global. We identify two types of controllability problem in MSC-based testing. It transpires that each type of controllability problem is related to a type of MSC pathology. <it>Controllability problems of timing</it> are caused by races but not every race causes controllability problems; <it>controllability problems of choice</it> are caused by non-local choices and not every non-local choice causes controllability problems. We show that some controllability problems of timing are avoidable and some controllability problems of choice can be overcome when testers have better observational power. Algorithms are provided to tackle both types of controllability problems. Finally, we show how one can overcome controllability problems using a coordination service with status messages based on algorithms developed in this paper.

Modern System-on-Chip (SoC) designs are becoming increasingly complex and powerful to meet the ever-growing computing demands form diverse application domains including the emerging Internet of Things (IoT). Given the widespread acceptance of SoCs in the electronic industry, it is critical to ensure their correctness from both functional and nonfunctional perspectives. SoC design complexity is increasing rapidly keeping pace with twofold increase in number of transistors every technology cycle. Drastic increase in design complexity has led to significant increase in SoC validation complexity. Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws (errors) during pre-silicon validation. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults including crosstalk, delay, and transient faults. Post-silicon validation is widely acknowledged as a major bottleneck in SoC design methodology—many recent studies suggest that it consumes more than 50% of an SoCs overall design effort (total cost) at 65nm technology. This problem is expected to get worse as the industry continues to move to even smaller geometries. This chapter provides a comprehensive overview of different challenges associated with SoC post-silicon validation and debug.

The System-on-Chip (SoC) design paradigm has revolutionized modern electronics by integrating an entire system into a single chip.SoCs combine various components like processors (CPU/GPU), memory, I/O interfaces, and peripheral units into one compact module, significantly reducing the size, cost, and power consumption of electronic devices.This seminar will explore the fundamental principles behind SoC design, its architecture, and key components, focusing on both the theoretical concepts and practical implementation strategies.We will delve into the design methodology of SoCs, examining top-down and bottom-up approaches, system integration, and verification.

Security is becoming an increasingly important parameter in current system-on-chip (SoC) design due to diverse hardware security attacks that can affect manufacturers, system designers or end users. To effectively address the security issues, design-time considerations, e.g. incorporation of design-for-security (DfS) features, are becoming essential. However, DfS measures for diverse security threats require specific design modifications to achieve target security level, which significantly increases design effort thus time-to-market, and usually incurs considerable design overhead. In addition, the general heterogeneous architecture of current SoCs makes many core-level DfS mechanisms unusable at SoC level. In this paper, we propose a centralized on-chip infrastructure IP for SoC security (IIPS), which alleviates the SoC designers from separately addressing different security issues through design modifications in multiple cores. It also provides ease of integration and functional scalability. We consider a specific implementation of IIPS that provides protection against: (1) scan-based attack for information leakage through low-overhead authentication; (2) counterfeiting attacks through integration of a Physical Unclonable Function (PUF); and (3) hardware Trojan attacks through a test infrastructure fortrust validation. To make the IP amenable for plug-and-play during SoC design, working protocols of the security functions are designed to comply with IEEE 1500 Standard for Embedded Core Test (SECT). Since IIPS resides outside the functional modules, it does not incur functional performance or power overhead. Simulations and experiments on example SoC designs validate the effectiveness of IIPS in providing protections against diverse attacks at a low hardware overhead.

This paper describes RaceCheck, a new verification program that audits System-on-Chip (SoC) designs for race logic design errors. The unique features of RaceCheck are: it can perform both static and dynamic analysis to reveal hard-to-detect race logic, and it makes use of SoC designs' structural and timing information to suppress false violations. The static race logic analysis is testbench independent, and can be used in all stages of a SoC development. The dynamic race logic analysis uses an event-driven simulation kernel to execute a SoC operations, and reports the exact times, locations and frequency of occurrences of all detected race logic in the design. RaceCheck complements traditional design verification tools to aid users achieve 100 % functional coverage of their new SoC products and time-to-market

Until now, simulation has been the primary approach for the functional verification of register transfer level (RTL) circuit descriptions written in a hardware description language (HDL). A finite state machine (FSM) coverage test can find all the bugs in a FSM design. However, this is impractical for large designs because of the state explosion problem. In this paper, we modify the higher-level FSM models used in other applications to replace the FSM model in the FSM coverage test. The state transition graphs (STGs) can be significantly reduced in this model, so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically, with little computation overhead. Experimental results show that it is indeed a promising functional test for FSMs.

In this modern technology era, in System on Chip (SoC) design, performance of processing units in computer is always on demand. By having hardware accelerators in computer system, core processor can offload task to it and this creates parallel execution to improve the processing speed. One of the functional blocks that are crucial in Hardware Accelerator's design is Storage Unit, which is used to keep data that is needed for processing or either the processed data. Under conventional hardware accelerator's design, the storage architecture is shaped to suit a certain processing algorithm and this introduced less flexibility in SoC design. In this paper, a novel design of storage architecture that is able to handle multiple accelerator engines and also modular to typical specification of hardware accelerators has been implemented.