An efficient functional coverage test for HDL descriptions at RTL

EPVD: An interactive protocol specification and validation environment in Estelle formal specification

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

In this paper, a video-oriented Differential Energy Watermarking scheme based on Finite State Machine (FSM) model against time-space tampering is suggested, which not only retains classical DEW algorithm's advantages dealing with space-domain attack, but also efficiently detects time-domain synchronous attack by using FSM model to produce inter-frame correlation. It is compound algorithm against time-space tampering. Experiments show that the watermarks keep robust to common intra-frame disturbance such as noise while its fragility to malicious inter-frame attack provides it effective directivity against synchronous attack. In addition, it performs well in invisibility, algorithm security and complexity.

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

Nowadays, Vending Machines are well known among Japan, Malaysia and\nSingapore. The quantity of machines in these countries is on the top worldwide.\nThis is due to the modern lifestyles which require fast food processing with\nhigh quality. This paper describes the designing of multi select machine using\nFinite State Machine Model with Auto-Billing Features. Finite State Machine\n(FSM) modelling is the most crucial part in developing proposed model as this\nreduces the hardware. In this paper the process of four state (user Selection,\nWaiting for money insertion, product delivery and servicing) has been modelled\nusing MEALY Machine Model. The proposed model is tested using Spartan 3\ndevelopment board and its performance is compared with CMOS based machine.\n

Syllable segmentation is an important process in the development of realistic visual speech synthesis for the Indonesian language. The process is to determine the syllables in a text by applying certain rules. In this study, we develop a rule-based syllable segmentation to convert Indonesian text into syllables. The rules are represented in the form of a finite state machine (FSM). The FSM model depends on the combination of vowels and consonants. The syllable peak indicated by the sound of a vowel, while the consonant sound represents a syllable valley. In a syllable, there is only a syllable peak, but the syllable valley can be more than one. Therefore, the number of syllables can be determined by looking at the vowels present in a word. The rules can be formulated by looking at the syllable pattern. The pattern can only be a vowel sound, a vowel with a consonant sound, and a vowel with two consonant sounds and others. The evaluation is done by entering Indonesian texts to the FSM model. The result shows that the FSM model could determine the syllables properly.

The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs.This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

This paper proposes an improved procedure to watermark soft Intellectual Property (IP) Cores at the Register Transfer Level (RTL) using Genetic Algorithms (GA). In order to merge the watermark signature and the IP Core's behavioral description, both are translated into Finite State Machines (FSM). The resulting FSM contains the watermarked IP Core maintaining its original functionality without disruption. However, a set of hanging states (a group of states not deeply embedded) has been observed and if any of these is deleted, the watermark could be removed and possibly the original IP Core functionality would not be disrupted, allowing for copyright infringements. Thus, a reduction procedure is applied to the watermarked design to reduce the number of hanging states, which to the best of the authors' knowledge has not been developed. Both FSM merging and reduction are NP-Complete problems. In this study, an improved objective function is proposed to accurately model the FSM reduction problem while applying GAs as optimization techniques at both stages. Empirical results show a significant improvement in terms of the number of final hanging states and watermark embedding strength as regards previous reported approaches.

Model-Based Testing (MBT) is a well-known technique that employs formal models to represent reactive systems’ behavior and generates test cases. Such systems have been specified and verified using mostly Finite State Machines (FSMs). There is a plethora of test generation algorithms in the literature; most of them are based on graphs once an FSM can be formally defined as a graph. Nevertheless, there is a lack of studies on analyzing cost and efficiency of FSM-based test generation algorithms. This study compares graph-based algorithms adopted to generate test cases from FSM models. In particular, we compare the Chinese Postman Problem (CPP) and H-Switch Cover (HSC) algorithms with the well-known Depth-First Search (DFS) and Breadth-First Search (BFS) algorithms in the context of covering all-transitions and all-transition-pairs criteria in an FSM. First, a systematic literature mapping was conducted to summarize the methods that have been adopted in MBT, considering FSMs. Second, the main methods found were implemented and analyzed on randomly-generated FSMs, as well as real-world models that represent embedded systems of space applications. To make comparisons, we considered analyses in terms of cost (time), efficiency (mutant analysis) and characteristics of the generated test suites (number of test cases, average length of test cases, largest and smallest test cases, standard deviation and distribution of test cases). In general, CPP presented the best results in terms of number of test cases and test suite size. In addition, CPP also presented low distribution of average length compared to other algorithms.

Context: Model-Based Testing (MBT) is a technique that employs formal models to represent reactive systems’ behav-ior and generates test cases. Such systems are mostly specified and verified using Finite State Machines (FSMs). There is a plethora of test generation algorithms in the literature. Most of them are graph-based once an FSM can be formally defined as a graph. Nevertheless, there is a lack of studies on analyzing cost and efficiency of FSM-based test generation algorithms. Objective: This study aims to compare graph-based algorithms employed to generate test cases from FSM models. In particular, we compare the Chinese Postman Problem (CPP) and H-Switch Cover (HSC) algorithms with the well-known depth-first and breadth-first searches algorithms in the context of covering all-transitions and all-transition-pairs criteria in an FSM. Method: First, a systematic literature mapping was conducted to summarize the algorithms that have been adopted in MBT, considering FSM. The main algorithms found were implemented and analyzed in different experiments. Results: CPP presented better results with the FSMs used in terms of number of test cases and test suite size. In addition, CPP also presented low distribution of average length compared to other algorithms.

Due to the globalization of Integrated Circuit supply chain, hardware Trojans and the attacks that can trigger them have become an important security issue. One type of hardware Trojans leverages the “don’t care transitions” in Finite-state Machines (FSMs) of hardware designs. In this article, we present a symbolic approach to detecting don’t care transitions and the hidden Trojans. Our detection approach works at both register-transfer level (RTL) and gate level, does not require a golden design, and works in three stages. In the first stage, it explores the reachable states. In the second stage, it performs an approximate analysis to find the don’t care transitions and any discrepancies in the register values or output lines due to don’t care transitions. The second stage can be used for both predicting don’t care triggered Trojans and for guiding don’t care aware reachability analysis. In the third stage, it performs a state-space exploration from reachable states that have incoming don’t care transitions to explore the Trojan payload and to find behavioral discrepancies with respect to what has been observed in the first stage. We also present a pruning technique based on the reachability of FSM states. We present a methodology that leverages both RTL and gate-level for soundness and efficiency. Specifically, we show that don’t care transitions and Trojans that leverage them must be detected at the gate-level, i.e., after synthesis has been performed, for soundness. However, under specific conditions, Trojan payload exploration can be performed more efficiently at RTL. Additionally, the modular design of our approach also provides a fast Trojan prediction method even at the gate level when the reachable states of the FSM is known a priori . Evaluation of our approach on a set of benchmarks from OpenCores and TrustHub and using gate-level representation generated by two synthesis tools, YOSYS and Synopsis Design Compiler (SDC), shows that our approach is both efficient (up to 10× speedup w.r.t. no pruning) and precise (0% false positives both at RTL and gate-level netlist) in detecting don’t care transitions and the Trojans that leverage them. Additionally, the total analysis time can achieve up to 1.62× (using YOSYS) and 1.92× (using SDC) speedup when synthesis preserves the FSM structure, the foundry is trusted, and the Trojan detection is performed at RTL.

A popular approach to reduce power consumption is to identify self-loops in a state transition graph (STG) of a finite state machine (FSM) followed by gating the clock with a suitable function to power down the circuit (implementation of the FSM) during the self-loop cycles. Although this approach is effective in circuits with plenty of self-loops, it fails for FSMs without self-loops. Since self loops may not be inherently present in a given FSM, we decompose it into interacting FSMs such that they have plenty of self-loops. In this paper we present a novel partitioning algorithm to decompose a given finite state machine. By using this approach, we could save upto 71% of the total power on circuits like fetch, where other techniques could not save any power.

The design idea of control and data separation is an effective means to realize the complex communication system, and the control part can usually be designed and realized by means of finite state machine (FSM). However, there is no effective method to realize the complex communication system based on finite state machine in the existing research. Aiming at the problem of the existing FPGA design and implementation methods with complex and non-universal communication protocol and algorithm design, a Flowchart based Finite State Machine (F-FSM) design and implementation method for FPGA is proposed, which significantly improves the FPGA development efficiency. This method takes the flowchart describing the complex communication system as input, divides the communication system into modules, and outputs the finite state machine transition diagram and transition matrix of the control module. This method can effectively shorten the design time of the communication system and its control module. Finally, an IP core encapsulated in FPGA is designed. This method can effectively improve the development efficiency of control module, improve the re-usability of control module and reduce the workload of code development.KeywordsFlowchartFinite state machineFPGA

Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test generation, and fault coverage. Finite state machines (FSMs) are commonly used for specifying controllers. FSMs may have shortcomings in modeling complex systems. With the introduction of X-machines, complex systems can be modeled at higher levels of abstraction. An X-machine can be converted into an FSM while preserving the level of abstraction. The fault coverage of a test sequence for an FSM specification provides a confidence level. We propose a fault coverage metric for an FSM specification based on the transition fault model, and using this metric, we derive the coverage of a test sequence. The article also presents a method which generates short test sequences that meet a specific coverage level and then extends this metric to determine the coverage of a test sequence for an FSM driven by an FSM network. We applied our FSM verification technique to a real-life FSM, namely, the fibre channel arbitrated loop port state machine, used in the field of storage area networks.

The goal of this paper was the development of a visual monitoring system for the management of stacking crane (moving within the aisles of the warehouse) using finite state machine (FSM). As usual, the implementation of a monitoring system required four preliminary steps: development of plotting FSM model, design of data exchange protocol, procession of operational monitoring data, visualization of a monitoring system. The paper was also presented form above contents. First, the operating characteristics of stacking cranes were analyzed to gain the operation control information and establish the plotting FSM model. Second, the data exchange protocol between the monitoring computer (MC) and the programmable logic controller (PLC) of stacking crane were designed based on the FSM model. Three, through the monitoring program, the operational data of stacking crane were gained and displayed in the visual monitoring platform. Finally, the visual monitoring system of stacking crane had been realized.