Test sequence generation for controller verification and test with high coverage

Finite state machines (FSM) are widely used in testing and verification of discrete event and hybrid systems. In order to guarantee fault coverage, various fault models and formal methods are utilized ranging from classical finite state machines (FSM) to logic circuits. The main problem for deriving an FSM-based test suite is the size of an FSM for real digital circuits, and thus, test engineers prefer to randomly derive a prefix of a test sequence and later on extend it with tests for hard detectable faults of a corresponding logic circuit. Usually at the latter step test sequences detecting hard detectable stuck-at faults are considered. In this paper, we are concerned about single functional faults, namely, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> , of a system of Boolean functions of the combinational part of a sequential circuit such as deleting a variable or a cube in a SoP which represents the ON-set or the OFF-set of a corresponding Boolean function and experimentally evaluate fault coverage of a corresponding complete test suite with respect to fault coverage of tests returned by other methods. The experimental results show high fault coverage of test suites complete with respect to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> and thus, it can be recommended to utilize such a test suite instead of a complete FSM-based test suite or to extend randomly generated test sequences for detecting <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> not killed with the prefix.

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

Until now, simulation has been the primary approach for the functional verification of register transfer level (RTL) circuit descriptions written in a hardware description language (HDL). A finite state machine (FSM) coverage test can find all the bugs in a FSM design. However, this is impractical for large designs because of the state explosion problem. In this paper, we modify the higher-level FSM models used in other applications to replace the FSM model in the FSM coverage test. The state transition graphs (STGs) can be significantly reduced in this model, so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically, with little computation overhead. Experimental results show that it is indeed a promising functional test for FSMs.

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log2 n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.

The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept of a semi-synchronous FSM that combines the benefits of both synchronous and asynchronous state machines. The result is a FSM which runs at high clock frequency, consumes very little power and can be implemented, verified and tested as a synchronous FSM. This concept has been used to design a PFM FSM in a field programmable gate array (FPGA) and in a 65 nm CMOS technology.

Synthesis of finite state machines for improved state verification

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

Minimizing Characterizing sets

Finite-state-machines (FSMs) model a variety of hardware and software systems. Unique input/output (UIO) sequences are used in generation of test sequences to verify that a machine is in an expected state, which in turn ensures system reliability. The paper presents an efficient algorithm for computing UIO sequences for completely and incompletely specified FSMs with binary inputs. Set of states which produces identical outputs for nonconflicting inputs are partitioned by incrementally constructing a successor tree. The transitions of FSM are modified to create a set of more specified transitions. This also resulted in constructing UIO sequences for an additional number of states. By a heuristic breadth-first search of successor tree, shorter test sequences are generated. In addition, classifying the nodes as ‘active’, ‘inactive’ and ‘dead’ and application of pruning rules and termination checks applied while partitioning the states reduced the search space and speeded up UIO-sequence construction. A chain-node search technique was used when successor tree failed to construct UIO sequences in some FSMs. The proposed algorithm, designated LANG, was tested with a large number of FSMs including the MCNC FSM benchmarks. To show the effectiveness of the proposed algorithm, results are compared with existing UIO-sequence-computation algorithms. The proposed algorithm computed shorter UIO sequences in negligible CPU time.

The problem of testing one-dimensional arrays made of sequential cells is addressed. Each cell is modeled as a finite state machine. Test sequence generation is accomplished using the unique input-output sequence method. The single cell fault model is adopted together with a functional model consisting of transition faults. Fault coverage is evaluated with respect to a gate level implementation of the cell. The conditions for controllability, observability and constant testability are defined. The added difficulty for such a testable approach stems from the fact that tests for sequential cells are composed of sequences of inputs instead of a single input combination (as for the combinational case). Guidelines for choosing test sequences which guarantee testability (and whenever possible, constant testability) without modification to the basic cell are introduced. >

A new fast PWM modulation strategy for power electric converter based on finite set state machine theory

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

Mutation testing from probabilistic and stochastic finite state machines

A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data portion can only be modeled by extended finite-state machines (EFSMs). However, infeasible paths due to the conflicts among the condition and action variables of EFSMs complicate the test generation process. We introduce a method enabling the automatic generation of realizable test sequences from a class of EFSMs. Algorithms to detect and eliminate conflicts caused by the interdependences among the variables of a class of EFSM models are presented. After all conflicts are eliminated from the EFSM graph, the existing FSM-based automated test generation methods can be used to generate feasible test sequences. Recently, these algorithms have been implemented as a software package called INDEEL. This methodology is applied to generate feasible tests for protocols such as ACA and MIL-STD 188-220. Current applications include IETF protocols and ASAP.

(Self-)reconfigurable finite state machine (FSM) had been introduced as a formal model to implement the sequential circuit which can be reconfigured during the operation. The reconfiguration is initiated by the external events or by the controller that generates the reconfiguration transitions. In this paper, we optimize the number of reconfiguration transitions required to reconfigure a given FSM into a new target FSM. A serious limitation of previously proposed techniques is that they depend on the number of essential transitions which are the different transitions between a given and a target FSMs. In this paper, we propose a new technique based on FSM decomposition to decompose a given and target FSMs into two sub machines. A part of essential transitions is implemented as a single decomposed submachine with the same functionality in two decomposed FSMs. This submachine is inactive and has no effect in the normal operation but reduces the number of essential transitions during the reconfiguration. We give a decomposition strategy, realize the proper hardware, and provide a set of experimental results that shows the reconfiguration transitions can be substantially reduced, in some cases up to 54%