An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors

Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for the execution of Java bytecodes and are widely used currently. The last method requires an embedded Java processor, picoJavaI or picoJavaII for instance. The picoJavaI and picoJavaII are simple pipelined processors with no ILP (instruction level parallelism) and TLP (thread level parallelism) supports. A so-called MAJC (microprocessor architecture for Java computing) design can exploit ILP and TLP by using a modified VLIW (very long instruction word) architecture and vertical multithreading technique, but it has its own instruction set and cannot execute Java bytecodes directly. In this paper, we investigate a processor architecture which can directly execute Java bytecodes meanwhile can exploit Java ILP and TLP simultaneously. The proposed processor consists of multiple slots implementing horizontal multithreading and multiple functional units shared by all threads executed in parallel. Our architectural simulation results show that the Java processor could achieve an average 20 IPC (instructions per cycle), or 7.33 EIPC (effective IPC), with 8 slots and a 4-instruction scheduling window for each slot. We also check other configurations and give the utilization of functional units as well as the performance improvement with various kinds of working loads.

Transistor budgets have been increasing at a very fast pace in the last years. This increasing transistor density will lead next generation processors to have a billion transistors available. It is the task of the computer architect to find the best way to use them.Out of order superscalar processors exploit parallelism at the finer grain, exploiting Instruction Level Parallelism (ILP). They issue multiple instructions per cycle, often in an order other than the specified by the programmer, using branch prediction and other speculative execution techniques in order to increase the available parallelism.Very Long Instruction Word (VLIW) processors also exploit parallelism at the instruction level, but they mostly rely on the compiler to detect the available parallelism. This increased compiler role allows a simpler design, and can be run at a faster clock rate, compensating for the loss of ILP.Chip Multiprocessors (CMP) join several narrow superscalar/VLIW components into a single processor, and mostly rely on the Thread Level Parallelism (TLP) for performance. The small and simple components can also run at a faster clock rate compensating for the loss of ILP, and significantly increasing throughput.Simultaneous Multithreaded (SMT) processors are based on wide superscalars, and exploit both ILP and TLP by issuing instructions from several different threads to the same pipeline, obtaining the benefits of TLP without sacrificing the ILP on single-threaded applications.For each of these options we will need to find the best balance between performance, design complexity, and power consumption among other factors. Also, the frontiers between them are not clear, and many intermediate design points can be found which leads to better/simpler/cheaper processors for the next generation of high performance computers.

Purpose — The purpose of this paper is to document in part the study that was conducted for a research project ASHRAE RP-1650, which investigates the training requirements for sustainable high-performance building (HPB) operations and maintenance (O&M). This paper documents the intent, procedures and findings of a portion of the research project, which includes a survey of O&M practices for high performance buildings in the industry. The purpose of the survey as reported in this paper was to confirm and refine the level of understanding of KSCs for operating HPBs as perceived by O&M personnel in the industry. The details of the survey and the results are presented in this paper. The survey was sent out to facility managers in the industry who are involved with the O&M of HPB systems and equipment. 221 facility managers were surveyed in this study. Design/methodology/approach — This study utilizes a concurrent mixed-method research, which considers both qualitative and quantitative responses. Findings — The study found that while most technicians were ‘moderately well' to ‘very well' trained for the configuration and components as well as the installation, repair and replacement of different high performance equipment and systems, they lacked essential knowledge to address issues such as: controls; tracking of variables; programming and operation of modulation devices implemented in high-performance systems and equipment. This finding implied a lack of ‘Systems Thinking' approach, which the study found to be pertinent and essential for the O&M of HPB systems and equipment. Originality/value — The study is utilized to identify gaps between the training requirements for O&M of HPBs identified from the literature review of the research project and the current industry practices. The identified gaps are valuable to develop learning objectives for training programs that are aimed to train personnel responsible for the O&M of HPBs.

Silicon photonics offers great opportunities to replace the bulky free-space systems with compact, highly integrated ones. However, dedicated optimization work is required to realize high performance systems for practical applications. This talk presents a library of optimized photonic components and a high-performance system as example.

With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction level parallelism (ILP) within significant constraints on power consumption and chip cost. Clustered VLIW (Very Long Instruction Word) architectures can be used to address this problem. Their clusters have to communicate by some mechanism to ensure that the data in one cluster can be used by other clusters as and when required. We selected four different mechanisms of inter cluster communication under the category of fully connected deadlock free networks. Then we designed and implemented the VLIW processors employing these mechanisms and analyzed them against various performance parameters-cycle time, cycle count overhead, instruction size and gate count. Also the effects of changing the data width and number of registers in a register file are analyzed.

Conceptual modeling is drawing more attention among researchers from many organizations and different disciplines including high-performance low-power multicore systems. As the popularity and demand grow, more processing power is required by the mission critical systems. Several chip vendors have developed teraflop computing systems (like Intel 80-Core Research Chip). Even though IBM offers the Roadrunner supercomputer, NSF and other research organization are looking for more powerful petascale computer system. In a petascale computer system, thousands to millions of processing cores are expected to work together using petabytes of memory to produce the expected performance. A high performance system like Roadrunner requires a very sophisticated power management system. No wonder, such a gigantic system costs millions of dollars. Conceptual modeling offers the opportunity to conduct research on complex and expensive systems in an inexpensive way. In this work, we address some key conceptual modeling issues and discuss a methodology to develop conceptual models of petascale computer systems. Important features of this methodology include data acquisition to improve accuracy by capturing the important details about the system under consideration and (system-to-) model abstraction to make the modeling manageable without eliminating any significant characteristics of the target system. We believe our findings help develop sound conceptual models of complex high performance petascale computer systems.

With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting important problems However, it has been thought that popular superscalar and VLIW world have difficult to obtain scalable improvement of effective performance in future because of the limitation of instruction level parallelism. To cope with this problem, a single chip multiprocessor (SCM) approach with multi grain parallel processing inside a chip, which hierarchically exploits loop parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism, is thought one of the most promising approaches. This paper evaluates effectiveness of the single chip multiprocessor architectures with a shared cache, global registers, distributed shared memory and/or local memory for near fine grain parallel processing as the first step of research on SCM architecture to support multi grain parallel processing. The evaluation shows OSCAR (Optimally Scheduled Advanced Multiprocessor) architecture having distributed shared memory and local memory in addition to centralized shared memory and attachment of global register gives us significant speed rip such as 13.8% to 143.8% for four processors compared with shared cache architecture for applications which have been difficult to extract parallelism effectively.

The effective performance of wide-issue superscalar processors depends on many parameters, such as branch prediction accuracy, available instruction-level parallelism, and instruction-fetch bandwidth. This paper explores the relations between some of these parameters, and more particularly, the requirement in instruction-fetch bandwidth. We introduce new enhancements to boost effectively the instruction-fetch bandwidth of conventional fetch engines. However, experiments strongly show that performance improves less for a given instruction-fetch bandwidth gain as the base fetch bandwidth increases. At the level of bandwidth exhibited by the proposed schemes, the performance improvement is small. This clearly brings to light potential relations between the fetch bandwidth and the other parameters. We provide a model to explain this behaviour and quantify some relations. Based on the experimental observation that the available parallelism in an instruction window of size N grows as the square root /spl radic/N, we derive from the model that the instruction fetch bandwidth requirement increases as the square root of the distance between mispredicted branches. We also show that the instruction fetch bandwidth requirement increases linearly with the parallelism available in a fixed-size instruction window.

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation

We have developed a novel solution-processed transparent thin film transistor technology based on sol-gel deposited SnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> semiconductor and ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric layers. The entire process is fully compatible with low-cost display glass substrates, and delivered unprecedented levels of performance. Devices with saturation mobility >; 100 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, Subthreshold swing of ~0.3V/decade, and operating voltage <;1.5 V were demonstrated. These record results represent a tremendous improvement in performance over the state of the art, and are an important step towards realizing low-cost, large area, high-performance systems on glass.

A high performance ECC hardware implementation with instruction-level parallelism over GF(2 163)

The number of Earth observation satellites from China increases dramatically recently and those satellites are acquiring a large volume of imagery daily. As the main portal of image processing and distribution from those Chinese satellites, the China Centre for Resources Satellite Data and Application (CRESDA) has been working with PCI Geomatics during the last three years to solve two issues in this regard: processing the large volume of data (about 1,500 scenes or 1 TB per day) in a timely manner and generating geometrically accurate orthorectified products. After three-year research and development, a high performance system has been built and successfully delivered. The high performance system has a service oriented architecture and can be deployed to a cluster of computers that may be configured with high end computing power. The high performance is gained through, first, making image processing algorithms into parallel computing by using high performance graphic processing unit (GPU) cards and multiple cores from multiple CPUs, and, second, distributing processing tasks to a cluster of computing nodes. While achieving up to thirty (and even more) times faster in performance compared with the traditional practice, a particular methodology was developed to improve the geometric accuracy of images acquired from Chinese satellites (including HJ-1 A/B, ZY-1-02C, ZY-3, GF-1, etc.). The methodology consists of fully automatic collection of dense ground control points (GCP) from various resources and then application of those points to improve the photogrammetric model of the images. The delivered system is up running at CRESDA for pre-operational production and has been and is generating good return on investment by eliminating a great amount of manual labor and increasing more than ten times of data throughput daily with fewer operators. Future work, such as development of more performance-optimized algorithms, robust image matching methods and application workflows, is identified to improve the system in the coming years.

It has been shown that control flow decisions often reduce the amount of fine-grain, or instruction-level parallelism in many computations. There exists various architectural solutions to this problem, such as branch prediction and speculative execution. Here we present an alternative solution, based on the use of partial evaluation for statically increasing the parallelism of a computation. In particular we explore the capability of a partial evaluator to remove control flow decisions.A partial evaluator is described, which specializes data flow graphs produced by a compiler for a fine-grained processor array. The data flow graphs can be viewed as the equivalent of a machine-code program for conventional processor, and consequently some aspects of the architecture can be taken into account by the partial evaluator.Results from the use of the partial evaluator show that it can significantly improve the performance of a computation. The performance improvement is partly due to improved parallelism, but mostly due to a reduce dynamic instruction count, i.e. a reduction in the number of operations executed.