An area efficient fully monolithic hybrid voltage regulator

This paper presents a miniaturized wide-input-range integrated reconfigurable three-level dc-dc voltage regulator. A three-level buck converter topology with zero-voltage switching (ZVS) is adopted to remove the dominant switching power loss under high-input-voltage condition, thereby enabling the converter to achieve high power efficiency in the megahertz range and reduce the required values of power passives. A constant-frequency adaptive-on-time $V^{2}$ control is proposed to not only regulate the output voltage, but also offer the flying capacitor self-balancing in the megahertz range and over a wide input range for improving the converter reliability. A body diode-based floating ZVS detector is also developed to enable full-ZVS operation of power transistors in high-frequency low duty-ratio conditions with $\leq 5$ ns ZVS turn-on delay. Implemented in a 120 V 0.5 $\mu \text{m}$ CMOS process, the proposed voltage regulator uses four 50 V on-chip power nMOS to support an input voltage from 12 to 100 V and regulates the output voltage at 10 V with a maximum output power of 5 W. The proposed regulator achieves a maximum power efficiency of 90% under the nominal 48 V input and 2 MHz switching frequency. Compared with the state-of-the-art counterparts, the proposed regulator provides >66 times and >2.6 times reductions in the inductance and the total capacitance, respectively.

SUMMARYThis paper presents the development of a new type of voltage regulator that can adequately maintain the voltage supplied to customers, dealing with the problem of voltage control that accompanies the widespread use of photovoltaic power generation systems. The newly developed device is a pole‐mounted voltage regulator consisting of a step‐down transformer that converts from high voltage to low voltage and a series transformer for voltage compensation. A demonstration test conducted at the CRIEPI Akagi Test Center confirmed that the voltage control function of the proposed voltage regulator is satisfactory, based on the proposed control algorithm. Simulation analysis, under the assumption of clustered installation of photovoltaic power generation systems, confirmed that the introduction of the proposed voltage regulator allows the system voltage to be adequately maintained and makes full photovoltaic power generation possible without suppressing the output. We anticipate that our proposed voltage regulator will be effective for adequately regulating the voltage in low‐voltage distribution systems and will effectively promote even more widespread photovoltaic power generation.

High-speed digital devices require multiple voltage and frequency domains to accommodate the core logic and the input/output (I/O) circuitry for multiple interfaces. In addition, some of these interfaces are programmable to various speeds and signaling modes and they require multiple power supply voltages. These requirements create complex power delivery and signal distribution solutions. This paper proposes a design methodology for fast transient point of load (POL) power distribution architectures for microprocessors and fast switching logic. This paper presents an efficient power distribution system (PDS) design methodology that models the load, its point of load power converter, and the transporting system so that the entire system can be efficiently implemented in circuit simulation as a complete integrated setup for design optimization. Models for the voltage regulator module (VRM) and its transient response and stability, the active load with multiple power supply domains, and the power planes are discussed in detail. System voltage noise margin budgeting is also emphasized.

기저대역 채널선택 필터는 외부의 잡음이나 공정상의 변화에 따라 각각의 통신 채널을 선택하기 위해 인가되는 제어 전압이 변동될 수 있다. 본 논문에서는 제어 전압을 일정하게 유지시키기 위해, 전류의 흐름을 감지하여 채널선택 필터의 차단주파수가 자동으로 조정되어 필터 동작이 원활하게 유지되면서 최소 면적을 갖는 전류 비교 방식 전압 안정화 회로를 설계하였다. Control voltage for baseband channel selection filter to select one of communication channels can be easily fluctuated according to external noise or variation of fabrication. In this paper, we design a voltage regulator with small chip area to keep control voltage constantly using current comparative method. Cut-off frequency of channel selection filter is automatically controlled by detecting current flow using the proposed voltage regulator.

A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement (SRE) circuit to provide large dynamic current for driving the pass device of the low-dropout (LDO) voltage regulator. What’s more, the proposed buffer, consuming small quiescent current over full load range, can work at low supply voltage, when comparing to conventional voltage buffer. A 1.2-V, 200-mA LDO with the proposed buffer has been designed in a 0.18-μm standard CMOS process. The low-voltage operation ability, high current efficiency and excellent transient response performance can be achieved. With a 1-μF ceramic output capacitor, the overshoot and undershoot of the output voltages are less than 20-mV when the load step changes between 1 and 200-mA in 100ns, while the current efficiency is up to 99.99% at full-load current.

Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted in recent years thanks to voltage and process scalability. However, achieving a fast response to a load change requires a conventional synchronous DLDO to either increase its sampling frequency with a large power overhead, or include a large output capacitor (COUT) with increased chip area and cost. Various control schemes have been proposed to mitigate these drawbacks. In synchronous designs, attempts have been made to employ more complex control algorithms to achieve faster response [1], and to replace the PMOS switch array with switched capacitors for reduced dynamic energy consumption [2]. On the other hand, asynchronous DLDOs with event-driven [3] and beat-frequency VCO-based structures [4] show promise across the key performance, power and area metrics. Recently, voltage regulators are also found to be useful in enhancing the resistance of cryptographic engines and processors against power and EM side-channel attacks (SCAs) [5]-[7], which are physical attacks representing a severe threat to mobile and embedded devices. Employing regulators for SCA defense is promising because they are already used in most systems and require no modifications to existing computing architectures and algorithms like other circuit-level defenses [8]-[9]. In this paper, we present a high-performance and SCA-aware DLDO leveraging the unique properties of the Edge-Chasing Quantizer (ECQ). The 65nm DLDO prototype achieves: 1) a 101.7mV droop and 506ns settling time after a 20mA, 0.1ns step load change, with only a 0.1nF capacitor; 2) a 0.018mm2 active area and 99.4% peak current efficiency; and, 3) more than 14000× improvement in power SCA resistance on a 128b AES engine, with 27.5% area, 19.4% power, and 4.54% performance overheads over a standalone AES, and negligible overhead when compared to an AES design integrated with conventional DLDOs.

This paper presents the design of multiple output power supply from AC power supply that is used as an input to this power supply system. As an Embedded system works on different voltage levels because the sub modules used in any embedded system required different voltage levels as per their specifications, so power supply proposed in this paper produces +15V, -15V, +5V, -5V, +3.3V, +5V Isolated voltage levels. The input for this power supply is 220 Volt AC supply. This AC supply is converted into DC supply of 48 volts but this range can be 36-72 volts. This power supply is capable of providing approximate 41W output power with 85% efficiency. The power supply design topology selected for this paper is flyback converter because flyback converter is an efficient method for generating multiple output voltage levels. This power supply is designed by utilizing low cost, highly efficient discrete components. This supply designed here can be used for almost all applications due to its versatile range of constant output voltage levels.

DC-DC converters are used to convert and regulate voltages depending on the requirement of the specific load. There are two types of DC-DC converter: (1) linear regulators and (2) switching regulators. A linear regulator has a small output voltage ripple but its power efficiency degrades when the difference between the input voltage and output voltage increases. On the other hand, the switching regulator has better power efficiency compared to the linear regulator. The switching regulator can convert wide range of input voltages while maintaining high power efficiency and it can also step-up voltages which a linear regulator cannot. The drawback for switching regulator is the need for control circuit that controls the switches and regulation. The switching regulator has also the problem of relatively larger output voltage ripple, which is not suitable for sensitive circuits. In this paper, a hybrid topology was proposed to combine the advantages of the two DC-DC converters. From the simulation of the three converters, the linear regulator only has an efficiency of 28.058% while the switching regulator and hybrid power converter have efficiencies of 49.0881% and 45.6753%, respectively. In addition, input voltages from 0.5V to 5V were tested on the three regulators that would result in a regulated output voltage of 1V. The linear regulator can only regulate voltages above 1V and the PMOS transistor used has a operating voltage of 2.5V which limits the upper voltage boundary of the linear regulator to 3.5V. The switching regulator can regulate wider range of input voltages but due to power loss across the converter, the switching regulator cannot produce a constant output voltage of 1V when the input voltage ranges from 0.5V to 0.7V. The three converters were designed and implemented in a 65nm CMOS process.

Developments in automotive (particularly hybrid-electric vehicles), aerospace, and energy production industries have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature silicon-on-insulator (SOI) process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various supply voltages and load currents. These supply voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuits is generated on chip via a voltage regulator producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator has been developed to meet the demands of a gate driver IC. The voltage regulator must be able to provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −25°C to 200°C, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation resulting in lower operating junction temperature. The designed voltage regulator has been successfully tested from −50°C to 200°C while demonstrating an output voltage variation of less than 10 mV under the full range of input voltage. Additionally, line regulation tests from 10 V to 30 V show a 12-ppm/V supply sensitivity. Full temperature and input voltage range tests reveal that the no-load supply current draw is within 17 mA while still providing in excess of 200-mA load current upon demand. Modifications to the existing design or off-chip biasing can widen the range of attainable output voltages and drive capabilities.

With significant growth in portable multimedia devices such as smartphones, application processors (AP) play a critical role for running various multimedia applications on these devices. By considering the power constraints of such devices, we often integrate reconfigurable processors (RPs) into APs. This is because RPs offer flexibility and good performance, thereby greatly improving the power efficiency for running these multimedia applications. Like many other processors, RPs also exploit the dynamic voltage/frequency scaling (DVFS) to improve their power efficiency. Owing to the platform cost constraints, however, these RPs are often integrated to low dropout (LDO) voltage regulators (VRs) instead of switching VRs. When compared with switching VRs, LDO VRs are very inexpensive; however, they suffer from considerable power loss when they are required to deliver a low output voltage. However, many previous studies focused on analyzing the power efficiency of various DVFS techniques only with regard to the processors and did not consider the negative impact of the VR power losses on the overall power efficiency of the platform. In this work, we quantitatively compare the power efficiency of a Samsung RP (SRP) adopting the race-to-halt technique with that of the SRP exploiting the DVFS supported by LDO VRs, by considering the effect of the VR power losses. Finally, we demonstrate that using the race-to-halt technique results in high power efficiency when compared with the DVFS in a commercial processor, by considering the VR power efficiency.

Fully integrated voltage regulators (FIVRs) can improve the performance and reduce the power consumption of a system-on-chip (SoC) by providing point-of-load voltage regulation with dynamic voltage scaling. The desirable attributes of FIVRs include high power efficiency, high power density, and fast transient response, which are difficult to achieve due to on-chip area constraint and parasitic effects. Low-quality and low-density on-chip inductors and capacitors are currently the main performance-limiting factors. This article presents a switched-inductor-capacitor (SIC) voltage converter that can operate more efficiently with compact on-chip air-cored metal-tracked inductors than existing step-down voltage converters. The SIC converter consists of an inductor, a flying capacitor, and three power switches, and it can provide fine-grained voltage regulation by using pulsewidth-modulation (PWM) control. The unique SIC converter topology eases the on-chip inductor integration by positioning the inductor at the input power supply and reducing the current stress of the inductor. A proof-of-concept fully integrated SIC voltage regulator is fabricated in a 65-nm CMOS process, with an area of 1.3 mm × 0.5 mm excluding pads. The output voltage can be regulated from 0.6 to 0.9 V given a 1.2-V input power supply. The output voltage ripple is below 56 mV over the entire range of output voltages and load currents. The peak power efficiency is 78% at an output of 0.9 V and 406 mA. The peak power density is 730 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the peak current density is 820 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

In this research project, an AC Cûk voltage regulator has been proposed for maintaining constant voltage across the load during wide range of input voltage fluctuations. The proposed AC Ck voltage regulator made of practical IGBT switches has been investigated for both manual and automatic control circuit. A fraction of the output voltage is taken as the input voltage of the control circuit and produce the error signal if any changes occur in the output voltage. The modified error signal is used to make PWM signals for switching devices as per output voltage of regulator. The PWM controls the ON/OFF time (Duty cycle) of switching devices (IGBTs) of the proposed regulator. As a result the regulator is maintaining a constant voltage across the load during any change in supply voltage. The simulation waveforms and the calculated total harmonics distortion (THD) values are compared with previously studied AC Buck-Boost regulator. The observed simulated waveforms of output voltage, output current and input current and THD values have been improved in case of proposed AC Cûk voltage regulator.

The single new energy power supply method has defects such as instability and discontinuousness. In order to improve the flexibility and stability of the power generation system and achieve the preferential utilization of new energy, this paper proposes a Boost type two-stage multi-input high frequency link's inverter with multi-winding simultaneous power supply, and the circuit topology, energy management control strategy (EMCS), high frequency switching process and active clamp circuit design of the inverter are studied and important conclusions are obtained. The circuit topology is composed of a two-level cascade of a multi-input Boost DC-DC converter and a Buck inverter. The front stage adopts the maximum power output phase-shifting pulse width modulation (PWM) control strategy with power limit. The rear stage adopts the single- polarity twice-frequency sinusoidal pulse width modulation (SPWM) control strategy. The maximum power output of multiple input sources is adjusted by controlling the DC bus voltage. The designed and developed 1kVA dual-input inverter prototype has excellent performance such as high frequency isolation between output and input and multiple input sources, small volume and weight, wide duty cycle adjustment range, high conversion efficiency, etc., which verifies the feasibility of circuit topology and EMCS.

This paper involves the development of three-dimensional microstructure formation and rapid growth copper electroforming technology in LIGA process. The important contributions involve using multiple power supplies in parallel and air-pressure assistance for the electroforming system to enhance the electroforming rate. The proposed method enhances the allowable applied current density in electroforming. Rapid growth rate is produced in the electroforming process and good deposition material properties are maintained. high cathode efficiency and short plating time were also achieved. The experimental graphs demonstrated these results. The LIGA process involved here to form plastic micromolds for three-dimensional electroforming is also introduced. Graphite film is applied as the x-ray mask membrane, producing successful PMMA exposure at 1mm thick. This proposed electroforming technology has practical applications compared with previous studies on current waveform, electrical potential, agitation method, and electrolyte composition.

This paper presents the design, simulation, and hardware implementation of a proposed method for improving efficiency of voltage regulator. Typically, voltage regulator utilized for noise-sensitive and low-power applications involves the use of a linear regulator due to its high power-supply rejection ratio properties. However, the efficiency of a linear regulator heavily depends on the difference between its input voltage and output voltage. A larger voltage difference across the linear regulator results in higher losses. Therefore, reducing the voltage difference serves as the key in increasing regulator's efficiency. This study hence proposes a pre switching regulator stage with positive voltage tracking cascaded to a linear regulator to provide an input voltage to a linear regulator which is slightly above the output of the linear regulator. The tracking capability is further required to provide the flexibility in generating different positive output voltage levels while maintaining high overall regulator's efficiency. Results from simulation and hardware implementation of the proposed system indicated the efficiency improvement of up to 23% in cases where an adjustable output voltage is deemed necessary. Load regulation performance of the proposed method also indicated better result compared to the case without the output voltage tracking method.