Design methodology for multiple domain power distribution systems

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency Scaling (DVFS) has been studied in past work as a mean to increase save power and improving the overall processor's performance while meeting the total power and/or thermal constraints. For such systems, power delivery limitations are becoming a significant practical design consideration, unfortunately this aspect of the design was almost ignored by many research works. This paper explores the various possible topologies to build a high end multi-core CPU and the available policies that maximize performance within the set of physical limitations. It evaluates single and multiple voltage and frequency domains and introduces a new clustered topology, grouping several cores together. A hybrid model, using measurements of a real CPU, cycle accurate simulator and an analytical model is introduced. The results presented indicate that considering power delivery limitations diverts the conclusions when such limitations are ignored. This paper shows that a single power domain topology performs up to 30% better than multiple power domains on light-threaded workload. In the fully threaded application the results divert. Clustered topology performs well for any number of threads.

Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.

This paper presents the design of multiple output power supply from AC power supply that is used as an input to this power supply system. As an Embedded system works on different voltage levels because the sub modules used in any embedded system required different voltage levels as per their specifications, so power supply proposed in this paper produces +15V, -15V, +5V, -5V, +3.3V, +5V Isolated voltage levels. The input for this power supply is 220 Volt AC supply. This AC supply is converted into DC supply of 48 volts but this range can be 36-72 volts. This power supply is capable of providing approximate 41W output power with 85% efficiency. The power supply design topology selected for this paper is flyback converter because flyback converter is an efficient method for generating multiple output voltage levels. This power supply is designed by utilizing low cost, highly efficient discrete components. This supply designed here can be used for almost all applications due to its versatile range of constant output voltage levels.

Summary form only given. Advanced power management is critical for SoC platforms targeting wireless mobile applications. In this tutorial the authors described power management strategies exploiting both basic and advanced power control mechanisms, as available in state-of-the-art, low power SoCs. Both low-leakage standby modes and variable-voltage, variable-frequency operations were considered. The opportunities and challenges in power management of SoC platforms with multiple power supply and clock frequency domains were discussed

Summary form only given. Advanced power management is critical for SoC platforms targeting wireless mobile applications. In this tutorial the authors described power management strategies exploiting both basic and advanced power control mechanisms, as available in state-of-the-art, low power SoCs. Both low-leakage standby modes and variable-voltage, variable-frequency operations were considered. The opportunities and challenges in power management of SoC platforms with multiple power supply and clock frequency domains were discussed

Increasing level of transistor integration with multiple voltage domains and power states, ever decreasing decoupling capacitance, fast load transients and the need for fine-grained spatio-temporal power management provide impetus for embedding distributed point of load (PoL) linear regulators deep within digital functional blocks of microprocessors and Systems-on-Chip (SoCs). This demands modularity in design as well as process and voltage scalability of such linear regulators. Digital linear regulators have emerged as an attractive counterpart to the traditional analog solutions. This paper presents the circuit implementation and a steady state response model of a discrete-time digital regulator with simulations and hardware measurements with an emphasis on the steady state oscillations. We develop parametric models to demonstrate design trade-offs for a stable steady state response.

Power distribution system design of the green well-off villages and small towns in East China is studied in this paper. Electricity load forecasting, power distribution and energy-saving systems design, effect of distributed energy accessing to the villages and small towns grid are studied. Finally, the advices are given on the power distribution system design of the green well-off villages and small towns.

Increasing on-chip temperature in SoC designs has reinforced the need for Dynamic Thermal Management (DTM). The conventional DTM techniques adopted in microprocessors based on DVFS are not suitable in the context of SoCs as they tend to have multiple voltage and frequency domains. In this paper we propose a reactive and a predictive DTM technique using bus arbitration. Based on the thermal profile the bus grants and hence the bus transactions are controlled. This regulates the data flow which reduces the activity in the functional units. The results show that the on-chip temperature can be maintained 3–5°C below the chip temperature threshold with a worst case performance penalty of 5% and a fast response time of at most 5 clock cycles. The hardware cost of implementing the proposed scheme is 3619.7μm2 in 45nm technology, which is less than 0.06% of the chip area. Apart from its simplicity, lower cost and effectiveness, the solution is non-intrusive on the design and scalable to many cores.

Multiple supply voltages are often utilized to decrease power dissipation in high performance integrated circuits. On-chip power distribution grids with multiple supply voltages are discussed in this paper. A power distribution grid with multiple supply voltages and multiple grounds is presented. The proposed power delivery scheme reduces power supply voltage drops as compared to conventional power distribution systems with dual supplies and a single ground by 17% on average (20% maximum). For an example power grid with decoupling capacitors placed between the power supply and ground, the proposed grid with multiple supply and multiple ground exhibits, respectively, 13% and 18% average performance improvement. The proposed power distribution grid can be an alternative to a single supply voltage and single ground power distribution system.

Current flow in power distribution systems inside an integrated circuit (IC), especially in VLSI and wafer-scale ICs, causes problems of voltage drop and metal migration, leading to logic malfunction, reduction in operating speed, and reduction in the expected life span of a chip. Accurate estimations of currents are needed to design the power distribution systems so that they will withstand the adverse effects of current surges. During fabrication or as a result of aging, the power distribution systems may break at some weak points. As a result, some parts of the systems may have to route excessive amounts of currents. A power distribution system should be designed so that, in the presence of a limited number of these breaks, the system will deliver currents to the macro cells without violating some prescribed limits on voltage drops and without causing metal migration. The author deals with estimating currents in the segments of power distribution systems under fault conditions and develops guidelines for designing the systems so that the voltage drop and metal migration constraints with respect to these current estimates will not be violated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of an advanced electric power distribution systems using seeker optimization algorithm

For future high-end server and workstation applications, it will be impractical for voltage regulator modules (VRMs) to draw power from the 12 V output of the silver box because the voltage bus will be too low to deliver the increasing high levels of power. Therefore, distributed power systems (DPSs) with buses of 48 V will be more feasible solutions for future high-end computers. This paper presents a novel multi-resonant push-pull (MRPP) topology for 48 V VRMs, based on methods for reducing the conduction loss and eliminating the body diode conduction and reverse-recovery losses of the synchronous rectifier. Two 48 V-1.2 V 70 A prototypes are built, and their efficiency is 86% at 1 MHz.

A hybrid voltage regulator module for an on-chip DC-DC voltage converter is proposed in this paper. The circuit is appropriate for point-of-load voltage regulation due to an ultra area efficient architecture. The proposed voltage regulator is a hybrid combination of a switching DC-DC voltage converter and a low-dropout regulator exploiting active circuitry rather than bulky passive devices within the filter structure. The proposed circuit can supply over 100 mA current while generating 0.9 volts from a 1.2 input voltage, exhibiting a high current efficiency of greater than 99%. The on-chip area is 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> which is 500 times smaller than a monolithic buck converter and four times smaller than an LDO. The proposed regulator provides a means for distributing multiple local power supplies across an integrated circuit while providing high current efficiency.

For a distribution power system, the loads are represented by kVA or P+jQ form in general. The so-called V-P formula(=Voltage-Power formula) composed of bus voltages and load power P,Q has been announced in recent publications. This paper introduces a step-by-step voltage calculation of each load point for a radial distribution power system using the simplified V-P formula without solving a simultaneous equation. Since each simplified V-P formula has at most two voltage variables, the voltages of load points can be obtained by the step-by-step method using a scientific calculator. The authors illustrate an example calculation for a distribution line with three P-Q load points to compare with the power flow computation. Calculation result by the proposed step-by-step method using simplified V-P formula has shown an acceptable error rate for use in the industrial fields.

Testability design of power distribution system considering noise immunity characteristics