An efficient control point insertion technique for leakage reduction of scaled CMOS circuits

As per the International Technology Roadmap for Semiconductors (ITRS) the leakage power is growing exponentially and is the major part of total power consumption in the integrated device. With the growing impact of subthreshold and gate leakage, static leakage contributes more and more towards the power dissipation in deep submicron nano CMOS technology. To overcome this problem several techniques has been proposed. In this paper we analyses the subthreshold leakage minimization techniques in circuit level. We propose a circuit technique named “Feedback Sleeper-Stack (FS-S)” for efficient leakage reduction in digital circuits. The proposed technique is compared with available leakage reduction techniques for subthreshold power, total power, delay and PDP (Power Delay Product). Of the available techniques, three power gating techniques are considered for comparison namely, Sleeper, Forced Stacking (FS) and Sleepy Stack (SS). Nominal supply voltage of 0.9V is selected and 32nm BSIM4 Predictive Technology Models (PTM) is employed in the analysis. ELDO Mentor Graphics tool is used for net list simulation.

The Graph-based Convex Clustering (GCC) method has gained increasing attention recently. The GCC method adopts a fused regularizer to learn the cluster centers and obtains a geometric clusterpath by varying the regularization parameter. One major limitation is that solving the GCC model is computationally expensive. In this paper, we develop efficient graph reduction techniques for the GCC model to eliminate edges, each of which corresponds to two data points from the same cluster, without solving the optimization problem in the GCC method, leading to improved computational efficiency. Specifically, two reduction techniques are proposed according to tree-based and cyclic-graph-based convex clustering methods separately. The proposed reduction techniques are appealing since they only need to scan the data once with negligibly additional cost and they are independent of solvers for the GCC method, making them capable of improving the efficiency of any existing solver. Experiments on both synthetic and real-world datasets show that our methods can largely improve the efficiency of the GCC model.

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCT's is always "near its cut-off voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC '91 benchmark circuits.

P-Bézier and P-Bspline curves – new representations with proximity control

An iterated improved reduced system (IIRS) procedure combined with sub-structuring scheme for nonclassically damped structural systems is presented. For dynamic analysis of such systems, complex eigenproperties are required to incorporate properly the nonclassical damping effect. In complex structural systems, the equations of motion are written in the state space from. Thus, the number of degrees of freedom of the new equations of motion and the size of the associated eigenvalue problem required to obtain the complex eigenvalues and eigenvectors are doubled. Iterated IRS method is an efficient reduction technique because the eigenproperties obtained in each iteration step improve the condensation matrix in the next iteration step. However, although this reduction technique reduces the size of problem drastically, it is not efficient to apply this technique to a single domain finite element model with degrees of freedom over several thousands. Therefore, for a practical application of the reduction method, accompanying sub-structuring scheme is necessary. In the present study, iterated IRS method combined with sub-structuring scheme for nonclssically damped structures is developed. Numerical examples demonstrate the convergence and the efficiency of a newly developed scheme.

We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology. We also show: (1) the optimum reverse body bias value reduces by /spl sim/2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by /spl sim/4X per generation under constant field technology scaling scenario. Optimum point occurs as a result of reduction in subthreshold leakage and an increase injunction band-to-band tunneling leakage with applied reverse bias. Therefore, new junction engineering techniques to reduce the bulk band-to-band tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

We present a self-adaptive algorithm for a new robust direct-sequence spread-spectrum system with integrated interference reduction capabilities to reduce narrowband- and broadband-interference regardless of their composition. Our reliable chip accumulation detector combines a comparatively low processing gain direct-sequence spread-spectrum system with an efficient interference reduction technique based on a simple adaptive nonlinearity employed prior to spread-spectrum demodulation. The information required for adjusting the adaptive nonlinearity to track the optimum state for efficient interference reduction is solely extracted from the received signal, primarily by exploiting level-crossing information. The resulting algorithm is fast, avoids loop structures, has no stability problems, and is easy and cheap to implement in hardware. The results of our Monte-Carlo simulations reveal that the proposed receiver always achieves the minimum symbol-error-probability, even under interference conditions that vary in the range of 40 dB.

Architectural innovations are reducing the dynamic power in ternary content addressable memories (TCAMs). Thus, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 41% leakage reduction over the conventional TCAM cell.

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

The high peak-to-average power ratio (PAPR) of time domain signals has been a major problem in orthogonal frequency division multiplexing (OFDM) systems, and thus various PAPR reduction algorithms have been introduced. Partial transmit sequence (PTS) is one of the most attractive solutions because of its good performance without distortion. However, it is considered as an impractical solution for the realization of high-speed data transmission systems due to its high computational complexity. In this paper, a novel PAPR reduction algorithm based on a tree-structured searching technique is proposed to reduce the PAPR with low complexity. In the proposed scheme, the computational complexity of searching process is decreased by adjusting the size of tree with two parameters, width and depth, while preserving good performance. The simulation results show that proposed scheme provides similar performance with optimum case with remarkably reduced computational complexity.

The existence of clutter in maritime radars deteriorates the estimation of some physical parameters of the objects detected over the sea surface. For that reason, maritime radars should incorporate efficient clutter reduction techniques. Due to the intrinsic nonlinear dynamic of sea clutter, nonlinear signal processing is needed, what can be achieved by artificial neural networks (ANNs). In this paper, an estimation of the ship size using an ANN-based clutter reduction system followed by a fixed threshold is proposed. High clutter reduction rates are achieved using 1-dimensional (horizontal or vertical) integration modes, although inaccurate ship width estimations are achieved. These estimations are improved using a 2-dimensional (rhombus) integration mode. The proposed system is compared with a CA-CFAR system, denoting a great performance improvement and a great robustness against changes in sea clutter conditions and ship parameters, independently of the direction of movement of the ocean waves and ships.

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

Impact of detailed chemistry and transport models on turbulent combustion simulations

In this paper, we present a new robust direct-sequence spread-spectrum concept with integrated interference reduction capabilities to reduce mixed narrowband- and broadband-interference. It combines robustness in the presence of strong interference of unknown composition with implementation simplicity and spectral efficiency. This is achieved by combining a comparatively low processing gain direct-sequence spread-spectrum system with an efficient interference reduction technique based on a simple adaptive nonlinearity employed prior to spread-spectrum demodulation. Our reliable chip accumulation technique allows to combine spectral efficiency with interference reduction capabilities comparable to traditional military spread-spectrum systems, which typically rely on a huge processing gain that is not affordable in commercial bandwidth-limited applications.

This letter presents a simple and effective peak reduction method to achieve a desired peak-to-average power ratio (PAPR). The method is called phase on demand in which a fixed phase vector is added to input vectors only if it helps reduce the peak of the orthogonal frequency-division multiplexing (OFDM) signal otherwise no phase is added. Repeated clipping and filtering is applied whenever the PAPR exceeds a desired value. To avoid sending side information about the phase, a maximum-likelihood phase detector is derived. Simulation results show that the new method is an efficient peak reduction technique for coded OFDM (COFDM).