A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Suppressing the leakage current in memories is critical in low-power design. Memory leakage suppression is critically important for the success of power-efficient designs, especially for ultra-low power applications. As the channel length of the MOSFET reduces, the leakage current in the SRAM increases. One method is to reduce the standby supply voltage (VDD) to its limit, which is the Data retention voltage (DRV), leakage power can be substantially reduced. This paper present a method based on controlling the leakage current by introducing the leakage controlled transistors in the SRAM. In the proposed model, we introduce two pairs of two leakage control transistors (a p-type and a n-type) within the SRAM cell for which the gate terminal of each leakage control transistor is controlled by the source of the other. This increases the resistance of the path from to ground, leading to decrease in leakage currents. The proposed SRAM cell cuts down the leakage current without increasing the dynamic power dissipation.

In this article, novel leakage control techniques are adopted in Feed-Through Logic (FTL) for low power high-speed designs. The FTL design has a unique feature; the outputs are partially evaluated before its input data arrive and quick final evaluation is performed as soon as input signals reach. However, FTL designs suffer from high leakage and standby current in static and dynamic modes which increase the total power dissipation. To resolve this issue leakage control techniques such as Leakage Control Transistor (LCT) and Self-Biasing Transistor (SBT) are adopted. It acts as a smart switch by virtual power gating, which reduces the voltage swing, causing the significant reduction in static and dynamic power dissipation. In addition to that mixed-mode ripple carry adder approach has been introduced using projected and basic designs. Simulation has been executed through PTM 45 nm technology using the T-spice simulator. The parametric analyses are performed to examine the reliability of the circuit through the capacitive load, supply voltage variations and the immunity to thermal noise demonstrating the effectiveness of the proposed technique. Simulation results have demonstrated that the proposed approaches achieve low power-delay product.

This contribution aims at incorporating leakage control transistors (LCTs) in differential cascode voltage swing logic (DCVSL) to reduce leakage and is named as L-DCVSL. The concept multi threshold is also introduced in LCTs and resulting static, dynamic and enhanced DCVSL variants are referred as MTL-DCVSL, MTL-dyDCVSL and MTL-EDCVSL. The performance at 90 nm, 65 nm, and 45 nm technology nodes is investigated using SymicaDE tool. Two input exclusive OR/NOR (XOR2/XNOR2) gate is used to illustrate the proposed technique due to its extensive use in arithmetic cores. The leakage current is examined in all the examples and it is found that leakage current decreases with scaling down of geometry. Maximum saving in leakage current is observed to be 81.27% while minimum is 44.18% for MTL-DCVSL. Similar observations for MTL-dyDCVSL and MTL-EDCVSL are (12.24%, 9.52%)/(33%, 66.04%) and (16.06%, 61.67%)/(37.11%, 78.45%) respectively for precharge/evaluate state. Effect of temperature is also investigated and it is found that leakage current in both static and dynamic configurations of DCVSL follows a directly proportional behaviour with respect to temperature.

This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation and leakage current was the main factor for the static power dissipation. The total power dissipation was calculated by the addition of static and dynamic power. From the simulated calculation we found that the consumption of the dynamic power (2.1 mW) was significantly less than the static power (219.75 mW) dissipation and the total power consumption was 221.85 mW. Xilinx-Virtex-II Pro XC2VP30 device is one of the commonly used programmable fabrics, which was employed here for all the calculation.

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techniques. At the process level, leakage reduction can be achieved by controlling the dimensions (length, oxide thickness, junction depth, etc) and doping profile in transistors. At the circuit level, threshold voltage and leakage current of transistors can be effectively controlled by controlling the voltages of different device terminals (drain, source, gate, and body (substrate)).

Architectural innovations are reducing the dynamic power in ternary content addressable memories (TCAMs). Thus, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 41% leakage reduction over the conventional TCAM cell.

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in /spl sim/67% leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.

As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restricted by the critical paths, and the saving of leakage current is limited. In this paper, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB to reduce the leakage current and cope with process variations. In the experimental result, our method is able to save leakage current from 41% to 46% as compared with design without body biasing technique. Under process variations, our method can save 40% to 49% leakage on fast circuits and 15% to 32% on slow circuits.

The impact of technology scaling on three run-time leakage reduction techniques (input vector control, body bias control and power supply gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25 um, 0.18 um, and 0.07 um technologies. HSPICE simulation results are estimations with various functional units and memory structures are presented to support a comprehensive analysis.

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

The increasing demand for small devices with additional requirements of low power consumption has been raised significantly from past decade. There are few more important parameters like speed, increasing operation frequency, and density of Complementary Metal-oxide Semiconductor circuits but power dissipation has become a critical parameter in such designs. Work done in this paper focuses on power, delay, and energy optimization of sequential digital Very Large Scale Integration (VLSI) circuits using Multi-Threshold CMOS (MTCMOS) technique. Different types of power, leakage, and energy reduction techniques have been discussed in this paper. The experiment is conduct with the power and ground gating techniques for MTCMOS. The virtual voltage of the power line and ground line is found by the power supplied to the circuit. 3-bit shift register has been designed with 32 and 45 nm technology.

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Design of half adder using integrated leakage power reduction techniques