New Technique for Reducing Sub-threshold Leakage in SRAM

This contribution aims at incorporating leakage control transistors (LCTs) in differential cascode voltage swing logic (DCVSL) to reduce leakage and is named as L-DCVSL. The concept multi threshold is also introduced in LCTs and resulting static, dynamic and enhanced DCVSL variants are referred as MTL-DCVSL, MTL-dyDCVSL and MTL-EDCVSL. The performance at 90 nm, 65 nm, and 45 nm technology nodes is investigated using SymicaDE tool. Two input exclusive OR/NOR (XOR2/XNOR2) gate is used to illustrate the proposed technique due to its extensive use in arithmetic cores. The leakage current is examined in all the examples and it is found that leakage current decreases with scaling down of geometry. Maximum saving in leakage current is observed to be 81.27% while minimum is 44.18% for MTL-DCVSL. Similar observations for MTL-dyDCVSL and MTL-EDCVSL are (12.24%, 9.52%)/(33%, 66.04%) and (16.06%, 61.67%)/(37.11%, 78.45%) respectively for precharge/evaluate state. Effect of temperature is also investigated and it is found that leakage current in both static and dynamic configurations of DCVSL follows a directly proportional behaviour with respect to temperature.

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCT's is always "near its cut-off voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC '91 benchmark circuits.

This paper proposes a novel low power 8T SRAM cell for write operation. In the proposed structure, two voltage sources VS1 and VS2 are connected with the bit line and the bit bar line, respectively. These voltage sources reduce the swing voltage and reduction in swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell. Also, two different leakage power reduction techniques called upper self controllable voltage level (USVL) and lower self controllable voltage level (LSVL) have been proposed and applied individually and in combination with the proposed 8T SRAM for the reduction of leakage current. Both the leakage current and power dissipation results are compared with those of conventional 6T and 7T SRAM cells reported in different literatures. Static noise margin is also analysed during write operation for stability purpose. The proposed SRAM cell has lesser leakage current in comparison to conventional 6T SRAM cell and also dissipates the least amount of power and yields better stability in comparison to both 6T and 7T SRAM cells. The authors use 45 nm CMOS technology with 0.5 volt power supply for simulation purpose. Microwind 3.1 software is used for schematic design and simulation.

Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design.

Design of half adder using integrated leakage power reduction techniques

To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.

Increased leakage current and device variability are posing major challenges to CMOS circuit designs in deeply scaled technologies. Static Random Accessed Memory (SRAM) has been and continues to be the largest component in embedded digital systems or Systems-onChip (SoCs). It is expected to occupy over 90% of the area of SoC by 2013 (Nakagome et al., 2003). As a result, SRAM is more vulnerable to those challenges. To effectively reduce SRAM leakage and/or active power, supply voltage (VDD) is often scaled down during standby operation (e.g. (Qin et al., 2004; Flautner et al., 2002; Bhavnagarwala et al., 2004; Wang et al., 2007)) and/or active operation (e.g. (Morita et al., 2006; Joshi et al., 2007)). For ultra-low-energy applications, SRAMs operating with VDD near/below the threshold voltage (VT) are also proposed (e.g. (Calhoun & Chandrakasan, 2007; Verma & Chandrakasan, 2008)). However, all SRAM functions, including read stability, write ability, access performance, and hold stability, are less reliable at lower voltage, which leads to the reduction of yield. The minimum supply voltage (Vmin) is limited by the lowest acceptable yield and determines the maximum achievable power reduction. Applying an underestimated Vmin will cause intolerable failures and decrease SRAM yield. On the other hand, applying an overestimated Vmin will waste power and energy. However, finding the optimum Vmin becomes difficult in the presence of global and local variations. In this chapter, we particularly explore SRAM Vmin during standby mode, i.e. data retention voltage (DRV). We first analyze the impacts of local/random and global/systematic variations on DRV, and then present new statistical and adaptive design methods to address those impacts. The goal of this chapter is to develop effective methods for achieving the best leakage power savings while maintaining the desired yield under variations.

In deep sub-100nm technologies, the exponential increase of static leakage current pose serious design challenges as we try to build efficient low power systems with faster memory cores. Consequently, it is imperative to design systems that adopt leakage control techniques during both standby and active mode. In the recent past, the size of memory cores also has been increasing at a very rapid pace to cope with the demands of high computing processors. Such large memory cores will lead to significant leakage power dissipation, as most of the devices will be in a dormant or standby mode. This study addresses the static current dissipation problem in an SRAM memory core, by implementing a combinatorial approach to reduce leakage current. In this approach we have combined multiple-Vth devices, high-oxide thickness devices and dynamic Vth techniques to reduce both subthreshold and gate-oxide leakage current. There is a ~60% savings in the total static current dissipated as compared to a conventional SRAM cell

Lowering the supply voltage can substantially decrease SRAM leakage power. There are several different approaches to determine the minimum standby voltage at which an SRAM array can preserve its data, also known as the array's Data Retention Voltage (DRV). The main goal of these approaches is to try and find the tail of the DRV distribution, since the worst SRAM bit cell sets the DRV of an entire memory block. The analytical approach concentrates on solving the sub-threshold voltage-transfer-characteristic equations of the core of a standard 6T bit cell. Another straight-forward method is running numerous Monte Carlo simulations to obtain the DRV at the required probability level. More advanced approaches based on static noise margin statistics remain valid for the extreme tails of the DRV distribution. Finally, the most accurate method is to use designated on-chip hardware to measure the DRV post-silicon fabrication. This paper overviews several recently proposed methods for DRV estimation and determination and discusses the advantages and trade-offs of these methods.

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test (BIST) unit, a DC-DC converter and some control logic. The proposed technique can be used to accurately measure the DRV to ensure the SRAM operates at its minimum energy point. The circuit was developed in 90nm technology and simulated using HSPICE. Monte-Carlo simulation of 100k samples determined the DRV as 150mV whereas the proposed technique showed that the DRV of the SRAM under test could be lowered to 80mV which would result in significant power savings.

In nanoscale SRAM design, issues related to cell stability, power dissipation, and delay are increasingly critical in the nanoscale SRAM design due to aggressive scaling of technology geometries. This paper presents a low-power and high-performance 8T SRAM cell design based on CNTFET technology for aerospace applications and the input-dependent (INDEP) technique. The proposed design addresses critical challenges in nanoscale SRAM, including high leakage currents, power dissipation, and stability issues. This architecture in comparison to conventional 6T and 12T SRAM cells brings notable performance gains. Superior stability is ensured by a read SNM of 402.5 mV, hold SNM of 402.2 mV, and write SNM of 423.6 mV. The design also shows faster operations, with a write time of 1.3 ns and read time of 1.8 ns, while maintaining energy efficiency with reduced read energy (18 aJ) and write energy (22 aJ). The static power consumption is also reduced to 0.7 µW with a considerable improvement compared with the traditional architectures. This work has set the basis for the 8T INDEP-CNTFET SRAM cell as an upcoming choice for next-generation energy-efficient memory applications in modern VLSI systems. Additionally, WSNM write access time is improved along with read access speed, which decreases and energy efficiency increases. These make the proposed 8T INDEP-CNTFET SRAM cell one of the promising solutions for future nanoscale memory applications.

There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell. Keywords: SRAM, stability, SNM, MTCMOS Cite this Article Nidhi Tiwari, Vaibhav Neema, Rangra Kamal J et al. Comparative Analysis of Different SRAM Cells Architecture at 70 nm. Journal of VLSI Design Tools & Technology. 2018; 8(2): 33–41p.