An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells

Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test (BIST) unit, a DC-DC converter and some control logic. The proposed technique can be used to accurately measure the DRV to ensure the SRAM operates at its minimum energy point. The circuit was developed in 90nm technology and simulated using HSPICE. Monte-Carlo simulation of 100k samples determined the DRV as 150mV whereas the proposed technique showed that the DRV of the SRAM under test could be lowered to 80mV which would result in significant power savings.

Static random access memory (SRAM) is one the most sensitive devices to radiation. It may often exhibit undesired reversals of memory bits, called single-event upsets or soft errors. Sensitivity to such undesired events is widely quantified with the parameter of cross sections, which varies from cell to cell due to process variations. Many efforts have been made to quantify such variations, most commonly using simulations that often become a hurdle especially for commercial-off-the-shelf SRAMs. In this regard, an analysis method is proposed to extract such variations easily from radiation test data. It relies on the data retention voltage, which is an electrical parameter associated with the static noise margin. This voltage can be measured on a desk without special circuits. The validity of the proposed method is experimentally demonstrated using SRAM fabricated in a 65-nm silicon-on-insulator technology, which was exposed to various high-energy heavy ions simulating the effects of galactic and terrestrial cosmic rays. Theoretical discussion provides further evidence, while revealing an interesting relationship between the data retention voltage and power supply voltage. This relationship suggests power-supply voltage tuning to deal with chip-to-chip variations in cross sections and also with similar variations caused by total-dose effects and aging effects such as negative bias temperature instability.

The design of the active RC integrator presented in this research utilizes a fully balanced technique and current-tunable frequencies to create the active RC integrator and reliable circuit. The circuit is made up of six npn bipolar junction transistors (BJT), six resistors (R), and a capacitor (C), with the fully balanced technique used to make the circuit structure uncomplicated and symmetrical with signal differencing. This approach results in a low number of internal devices in the circuit, making it an attractive option for integrated circuit (IC) development. One of the key features of the fully balanced current-tunable active RC integrator is its ability to be frequency-tunable with bias current (If). This feature enables the circuit to be used in a variety of applications, including filter circuits, communication signal generators, instrumentation signal generators, and various automatic controls. The fully balanced design also ensures that the circuit is stable and robust, even in the presence of device parameter variations. To evaluate the performance of the active RC integrator, simulations were conducted using Pspice.
 The results show that a fully current-tunable active RC integrator can be precisely tuned with the active bias to a value consistent with the theoretically calculated value. This demonstrates the efficiency and reliability of the circuit design and simulation method. The Monte Carlo (MC) method was also used to analyze the circuit performance in cases where the resistor (R) and capacitor (C) device had a 10 percent error and the transistor gain (β) was set to an error of 50 percent. The MC analysis showed that the phase shift (degree) and magnitude (dB) of the circuit were stable, and the circuit's performance was not significantly impacted by the device parameter variations. This further demonstrates the robustness and versatility of the fully balanced current-tunable active RC integrator design. Finally, harmonic distortion was evaluated to confirm the performance of the designed and developed fully balanced current-tunable active RC integrator. The results showed low levels of harmonic distortion, which indicates that the circuit is suitable for high-performance applications that require low distortion

Importance sampling (IS) is a powerful Monte Carlo (MC) methodology for approximating integrals, for instance in the context of Bayesian inference. In IS, the samples are simulated from the so-called proposal distribution, and the choice of this proposal is key for achieving a high performance. In adaptive IS (AIS) methods, a set of proposals is iteratively improved. AIS is a relevant and timely methodology although many limitations remain yet to be overcome, e.g., the curse of dimensionality in high-dimensional and multi-modal problems. Moreover, the Hamiltonian Monte Carlo (HMC) algorithm has become increasingly popular in machine learning and statistics. HMC has several appealing features such as its exploratory behavior, especially in high-dimensional targets, when other methods suffer. In this letter, we introduce the novel Hamiltonian adaptive importance sampling (HAIS) method. HAIS implements a two-step adaptive process with parallel HMC chains that cooperate at each iteration. The proposed HAIS efficiently adapts a population of proposals, extracting the advantages of HMC. HAIS can be understood as a particular instance of the generic layered AIS family with an additional resampling step. HAIS achieves a significant performance improvement in high-dimensional problems w.r.t. state-of-the-art algorithms. We discuss the statistical properties of HAIS and show its high performance in two challenging examples.

In this paper, we present a variance minimization (VM) procedure for rare event simulation in tandem queueing networks. We prove that the VM method can produce a zero variance. The VM method is suitable to compute optimal importance sampling (IS) parameters for small scale tandem networks. For large scale tandem networks we propose a sub-optimal IS (SOIS) method, which projects the optimal biased transition probabilities of the corresponding small scale system into those of a large scale system. In other words, we establish an efficient IS method for a large scale system by zooming into a small scale system and then projecting our findings into the large scale system. The numerical results show that our SOIS method can produce accurate results with very short CPU time, while many other methods often require much longer.

An efficient time-dependent (TD) Monte Carlo (MC) importance sampling method has recently been developed [G. Tao and W. H. Miller, J. Chem. Phys. 135, 024104 (2011)] for the evaluation of time correlation functions using the semiclassical (SC) initial value representation (IVR) methodology. In this TD-SC-IVR method, the MC sampling uses information from both time-evolved phase points as well as their initial values, and only the "important" trajectories are sampled frequently. Even though the TD-SC-IVR was shown in some benchmark examples to be much more efficient than the traditional time-independent sampling method (which uses only initial conditions), the calculation of the SC prefactor-which is computationally expensive, especially for large systems-is still required for accepted trajectories. In the present work, we present an approximate implementation of the TD-SC-IVR method that is completely prefactor-free; it gives the time correlation function as a classical-like magnitude function multiplied by a phase function. Application of this approach to flux-flux correlation functions (which yield reaction rate constants) for the benchmark H + H(2) system shows very good agreement with exact quantum results. Limitations of the approximate approach are also discussed.

This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods - based upon calibration runs in circuit simulators - to determine noise susceptibility in the presence of variations in process, design, and environmental parameters (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , and W) are described. Such analytical methods can be used not only to accurately estimate the impact of variability on noise robustness, but also to optimize designs for noise robustness

In this paper we propose a new importance sampling (IS) scheme to estimate the low error-rate performance of LDPC codes over a Rayleigh fading channel. It biases the Rayleigh fading distribution as well as the noise distribution in order to improve the quality of estimation. The proposed IS scheme is compared with the Monte-Carlo (MC) simulator and other IS schemes in terms of its efficiency and accuracy. Numerical results show that the proposed IS estimator is much more efficient than the MC estimator and other IS estimators from the viewpoint of the required simulation time. Furthermore, the proposed IS scheme provides a more accurate performance estimation of LDPC codes over a Rayleigh fading channel with only a limited simulation time than other IS schemes.

This paper illustrates the use of the Importance Sampling (IS) technique for efficient simulation of Orthogonal Frequency Division Multiplexing Systems operating over frequency selective fading channels with equalization. In order to achieve higher estimator variance reduction gains, the proper biasing procedure for time domain noise density function and the way of un-biasing the error count at the receiver in frequency domain are shown. Further, the optimum biasing parameters for conventional importance sampling (CIS) and improved importance sampling (IIS) methods are obtained. It is demonstrated, through simulations, that the proposed methods can provide extensive gains in estimator variance reduction and runtime saving compared to the conventional Monte-Carlo (MC) simulations.

Massively repeated structures such as SRAM cells usually require extremely low failure rate. This brings on a challenging issue for Monte Carlo based statistical yield analysis, as huge amount of samples have to be drawn in order to observe one single failure. Fast Monte Carlo methods, e.g. importance sampling methods, are still quite expensive as the anticipated failure rate is very low. In this paper, a new method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. The proposed method improves the performance for both stages in importance sampling, i.e. finding the distorted probability density function, and the distorted sampling. Experimental results show that the proposed method is 1e2X∼1e5X faster than the standard Monte Carlo approach and achieves 5X∼22X speedup over existing state-of-the-art techniques without sacrificing estimation accuracy.

A new global variance reduction technique based on pseudo flux method

Analysis of inconsistent source sampling in monte carlo weight-window variance reduction methods

When estimating the bit error rate (BER) of communications systems using Monte Carlo (MC) simulation, importance sampling (IS) may be a powerful method for reducing simulation runtimes. The paper presents an IS technique combined with error event simulation in order to evaluate efficiently the performance of Viterbi decoding used with a binary nonsymmetric channel and with a binary erasure channel. Two biasing approaches are employed, stationary and nonstationary models. Comparative results between the two models and traditional MC methods are presented.

Extensive research has been conducted on a statistical timing analysis of digital integrated circuits in the existence of statistical parameter variations. However, the proposed methods either lack accuracy or efficiency, which avoids coming up with an industry standard tool. Despite this fact, there is a certain consensus that Monte Carlo (MC) methods are accurate, so that they are called golden. In this paper, we propose novel techniques to combine control variates with importance sampling in order to come up with a new timing yield estimator as accurate as SPICE-based standard MC (STD-MC) but much faster. The performance of three different estimators, two of which are proposed in this paper, is compared through experiments, and the results show that the precise SPICE simulation-based STD-MC method can be accelerated about $260\times $ on the average without sacrificing any accuracy.

In epidemiological and occupational health studies it is not uncommon to find that the distribution of exposure to a quantitative risk factor is highly skewed, as, for example, when most of a population suffers little or no exposure to a hazardous agent while a small subset receives very high exposures. As a result the asymptotic significance levels of conditional tests for monotone trends in rates or proportions can be profoundly anticonservative when applied to small or even moderate numbers of events. Monte Carlo (MC) estimation of observed levels of significance (”p-values”) provides a useful method for accurately assessing statistical significance in such situations. We describe a simple technique of importance sampling (IS) which can greatly improve the efficiency of MC estimation in this setting. Use of the IS technique is illustrated with data regarding cancer mortality among atomic bomb survivors.