Process Variation Aware Analysis of SRAM SEU Cross Sections Using Data Retention Voltage

Scaling of technology has a severe impact on the reliability of semiconductor devices. Negative bias temperature instability (NBTI) is a dominant factor in reliability degradation in nano‐scale technology. It is an aging phenomenon, which degrades the p‐channel metal oxide semiconductor (PMOS) transistors over time. A large area of the system on chip is covered by static random access memory (SRAM) and thus the overall system performance greatly depends on the stability of SRAM. In this paper, we evaluate the effect of NBTI on 6T SRAM cell performance for the stress period of 10 years. The simulation results show that the write margin is increased by 3.356% whereas hold static noise margin (SNM), read SNM, and standby leakage current is reduced by 6.53%, 23.86%, and 13.42%, respectively. We also present a series diode‐connected current mirror‐based linear and sensitive NBTI monitoring circuit using n‐channel metal oxide semiconductor (NMOS) transistors only. Continuous monitoring of the NBTI effect without any bias generator or control circuit is vital for the proposed sensor circuit. We have developed the electrical equivalent model and mathematical model of the proposed sensor for the fair comparison of results obtained through simulation and modeling. The sensitivity of the sensor is 40.6 μV/nA, and the sensor output voltage has a temperature variation of 20 μV/°C.

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static power by the other side, OCAS circuitry is powered-off during idle periods. SPICE simulations in a 65nm CMOS technology demonstrate the high sensor sensitivity to detect early aging states and so, guarantying high memory reliability. Furthermore, area overhead due to sensor insertion is almost negligible.

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V TH transistors age faster than the high V TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V TH with technology scaling. Also NBTI effect is more significant at higher temperature.

This paper compares six different 8T SRAM bitcells targeting different design space requirements - such as reliability and low power/energy - for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of high-threshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra- and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy.

We present a comparative analysis of a fabricated 65nm CMOS static random access memory (SRAM) chip and commercial SRAM chips in terms of security vulnerability. The security vulnerability is defined as the leakage of information due to the data imprinting effect of the SRAM. There are three main features in this evaluation. First, a complete security vulnerability evaluation flow is proposed to stress the SRAM chips for accelerating the negative-biased temperature-instability (NBTI) degradation, i.e. data imprinting effect, and hence to reveal the stored data of image. Second, the evaluation quantifies the percentage of revealed data, i.e. leakage of information for the comparison of tested SRAMs. Third, the image is reconstructed from the revealed data to illustrate the security vulnerabilities of tested SRAMs. We perform the security vulnerability evaluation on the 65nm CMOS SRAM chip and 4 commercial SRAM chips, namely Alliance, Lyontek, Cypress and AMIC under stressing of high voltage and high temperature. From the experimental results, the stored data is significantly revealed in the deep-submicron (≤90nm) CMOS SRAM chips, i.e. fabricated 65nm CMOS (16.1%), Alliance (16.2%) and Lyontek (21%). After reconstructing the images, they can be identified in the 65nm CMOS, Alliance, Lyontek SRAMs, but remain as random states in the Cypress and AMIC SRAMs.

This paper investigates the static noise margin (SNM) of ultrathin-body (UTB) SOI SRAM 6T/8T cells operating in the subthreshold region using analytical solutions of Poisson's equation validated with TCAD simulations. An analytical framework to calculate the SNM for UTB SOI SRAMs operating in the subthreshold region is presented. Our results indicate that for improving both read SNM (RSNM) and write SNM (WSNM), the back-gating technique is more effective in the subthreshold region than in the superthreshold region. The 6T UTB SOI subthreshold SRAM cell with the back-gating technique by increasing the strength of the pull-up transistors and decreasing the strength of the pass-gate transistors shows comparable RSNM with the 10T bulk subthreshold SRAM and an improvement in RSNM variation. Due to better electrostatic integrity, the back-gating technique (pull-up transistors with positive back-gate bias, pull-down/pass-gate transistors with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows a limited improvement on RSNM and has no benefit on the SNM variability for the subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2times larger than the 6T SRAM cell in the subthreshold region. Both negative bit-line voltage (VBL) and boosted word-line voltage (VWL) are more effective than lower cell supply voltage to improve WSNM, and negative VBL shows a larger improvement in WSNM than boosted VWL.

In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently controlled gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

In this paper, statistical variability and different levels of BTI degradation are introduced into a compact model by statistical parameter extraction. Static Random Access Memory (SRAM) is used to test the compact model and to investigate the effects of MOSFET statistical variability and degradation at circuit level. Statistical distributions of Static Noise Margin (SNM) under different scenarios representing various degradation levels as well as mismatch levels between ‘on’ and the rest of the SRAM cell transistors are compared to investigate their impacts on SRAM stability. A surface response model of the dependence of the mean and standard deviation of SNM on circuit ageing and transient stress is also developed to quickly evaluate SRAM stability at arbitrary degradation levels.

Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable.

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

WITHDRAWN: Comparative analysis on low power SRAMs

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

Bias Temperature Instability (BTI) is posing a major reliability challenge for today's and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write Trip Point (WTP); while the aspects investigated include BTI impact dependence on the supply voltage, cell strength, and design styles (6 versus 8 Transistors cell). A comparison between FinFET and planar CMOS based SRAM cells degradation is also covered. The simulation performed on FinFET based cells for 108 seconds of operation under nominal Vdd show that Read SNM degradation is 16.72%, which is 1.17X faster than hold SNM, while WTP improves by 6.82%. In addition, a supply voltage increment of 25% reduces the Read SNM degradation by 40%, while strengthening the cell pull-down transistors by 1.5× reduces the degradation by only 22%. Moreover, the results reveal that 8T cell degrades 1.31× faster than 6T cell, and that FinFET cells are more vulnerable (~ 2×) to BTI degradation than planar CMOS cells.

Radiation-induced single-event upsets (SEUs), or soft errors, cause a significant threat to the reliability of nanoscale memories. In this paper, we have proposed a 10-T radiation-hardened SRAM cell with exceptionally high radiation tolerance. The proposed cell has significantly better performance in terms of radiation robustness as compared to other existing radiation-hardened SRAM cells. Comparisons of several hardened memory cells in terms of access time (read access time and write access time), stability (read static noise margin, write margin, and hold static noise margin), power consumption (read power, write power, and hold power), and layout area is done. From these comparisons, it can be concluded that the proposed cell has better or comparable performance for all the parameters, except for write access time (TWA). The write access time is longer for the proposed cell as compared to other comparison cells. Furthermore, the effect of supply voltage variation has also been studied by calculating and comparing all the parameters at different supply voltages. Monte Carlo simulations are also used for some of the parameters to evaluate the effects of process, voltage, and temperature (PVT) variations.