WITHDRAWN: Comparative analysis on low power SRAMs

The growing demand for low-power static random access memory (SRAM) cells in Internet of Things (IoT) devices has led to the development of various SRAM cell topologies that minimize power consumption while maintaining performance and stability. In this paper, we have analyzed various SRAM designs based on different parameters, such as power dissipation, delay, area, energy, and stability. It is observed that 6T SRAM cell, consisting of six transistors, is the most widely used topology due to its simplicity and low area requirements. However, larger cells such as 8T,9T, and 10T have been developed to improve stability and reduce power consumption, although they require more area. It has been observed8 T work better for read delay while 9T works better for 9 Scaling down SRAM cells to smaller feature sizes presents challenges in maintaining stability and reliability while minimizing power consumption.

Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable.

High-performance Low-power static random access memories (SRAMs) are required in many battery-powered applications. This paper presents a process temperature frequency (PTF) adaptive voltage scale technique to reduce power. In the self-adaption phase, the optimal supply voltage is chose automatically according to PTF. So a significant reduction in power consumption can be achieved. Moreover, SRAMs can be accessed normally when they are in the self-adaption phase. Simulation results illustrate that saved power is more than 60% when supply voltage is changed from 1.2V to 0.7V. The optimal supply voltage is dependent on different process corners, temperatures and operating frequencies.

Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

SRAM (Static Random Access Memory) has become a major key component in many VLSI Chips, due to its high storage density and quick access time, it has become a popular data storage device. SRAM has played a significant role in the global VLSI sector. Due to the significant increase of low power and low voltage memory systems in recent times, SRAM has been prioritised in the research sector. This is owing to the increased demand for high-end devices, IC memory cards, and other communication devices, as well as the advancement of portable battery-operated devices. The power and area of a low-power 6T SRAM cell design are assessed in this research. This work describes the design and implementation of a 6T SRAM cell in standard CMOS process technology at 180nm, 90nm and 45nm nodes. In the Cadence Virtuoso Software, this simulation was run. The Static Noise Margin has been used to analyse the performance of SRAM cells. The schematic, transient simulation, and DC analysis are all included in this work.

This paper investigates the static noise margin (SNM) of ultrathin-body (UTB) SOI SRAM 6T/8T cells operating in the subthreshold region using analytical solutions of Poisson's equation validated with TCAD simulations. An analytical framework to calculate the SNM for UTB SOI SRAMs operating in the subthreshold region is presented. Our results indicate that for improving both read SNM (RSNM) and write SNM (WSNM), the back-gating technique is more effective in the subthreshold region than in the superthreshold region. The 6T UTB SOI subthreshold SRAM cell with the back-gating technique by increasing the strength of the pull-up transistors and decreasing the strength of the pass-gate transistors shows comparable RSNM with the 10T bulk subthreshold SRAM and an improvement in RSNM variation. Due to better electrostatic integrity, the back-gating technique (pull-up transistors with positive back-gate bias, pull-down/pass-gate transistors with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows a limited improvement on RSNM and has no benefit on the SNM variability for the subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2times larger than the 6T SRAM cell in the subthreshold region. Both negative bit-line voltage (VBL) and boosted word-line voltage (VWL) are more effective than lower cell supply voltage to improve WSNM, and negative VBL shows a larger improvement in WSNM than boosted VWL.

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

Static Random Access Memory (SRAM) is volatile and uses latching flip-flops to store each bit. To make SRAM work as non-volatile memory (NVM), memristor-based SRAM is a feasible choice mainly due to its high-speed operation and low power consumption. In this paper, the operational characteristics of 4T2M SRAM have been studied based on three different memristor models developed by Biolek et al. (2009), Joglekar and Wolf 2009, and Prodromakis et al. (2011), and comparative performance analysis has been made to assess its adaption to NVM. These three different models are compared in terms of delay, power consumption, and static noise margin. From the simulation, it has been observed that Biolek 4T2M SRAM produces better performance in write delay calculation scoring 0.873 ns when ‘0’ is written and 0.166 ns when ‘1’ is written. This model also provided a low power consumption value compared to other models. However, ternary plot analysis finds that Prodromakis is performing in average better in all positive traits. All the simulations are done in LTSpice and the transistor uses TSMC 180 nm CMOS technology.

The standby current at device off-state is investigated against the measuring mode in 6-T and low-power static random access memory (SRAM) device with short gate length of 0.12 µm and high density of 32 M-bit. It can be found that there is the difference of the standby currents between initial and D0 modes and this discrepancy in the standby current is closely related to the leakage current of cell n-type metal-oxide semiconductor field-effect transistor (NMOSFET), especially pull-down transistor. This discrepancy in the standby currents among the measuring modes can be explained with the characteristic of the cell latch using its dependence on the leakage current of pull-down transistor and it will be shown that the cell spontaneously moves to minimize the standby current.

The growing demand for high-performance and energy-efficient memory has accelerated the development of low-power static random-access memory (SRAM) architectures, which form a critical component of modern system-on-chip (SoC) designs. This paper presents a comprehensive analysis of a novel 11T SRAM cell, with a strong emphasis on physical design considerations. The proposed 11T cell introduces a dedicated read line and a transmission gate in place of conventional pass transistors, resulting in enhanced read/write stability and reduced power consumption. The design is implemented and evaluated using Cadence Virtuoso with TSMC 65 nm CMOS technology. Simulation results confirm that the proposed 11T cell achieves 39.56% improved write static noise margin (SNM) and 11.50% lower power dissipation and 6.7% higher write speed compared to stack transistor-based 11T architecture. Additionally, a comparative analysis involving 6T, 8T, conventional 11T, and the proposed 11T SRAM cells was performed using both TSMC 65 nm and UMC 65 nm technology nodes. The results demonstrate that TSMC 65 nm technology yields superior performance over UMC. Post-layout simulations further validate the design’s stability in the presence of parasitic effects, with all evaluations conducted at a supply voltage of 1.2 V.

In this paper, statistical variability and different levels of BTI degradation are introduced into a compact model by statistical parameter extraction. Static Random Access Memory (SRAM) is used to test the compact model and to investigate the effects of MOSFET statistical variability and degradation at circuit level. Statistical distributions of Static Noise Margin (SNM) under different scenarios representing various degradation levels as well as mismatch levels between ‘on’ and the rest of the SRAM cell transistors are compared to investigate their impacts on SRAM stability. A surface response model of the dependence of the mean and standard deviation of SNM on circuit ageing and transient stress is also developed to quickly evaluate SRAM stability at arbitrary degradation levels.

In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently controlled gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents the design and simulation of a 16-bit $\times 32$ -bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit $\times 32$ -bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of a conventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit $\times 32$ -bit SRAM is generalized and an $n\times 16$ -bit $\times 32$ -bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared with the SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.