Expression of Concern: Parameter-Variation-Aware Analysis for Noise Robustness

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.

The possibility of using the adaptive capacity of the larvae of marine invertebrates under the variation of environmental parameters was studied as a sensitive test of sea water pollution. The object of the research was the larvae of Cryptonatica janthostoma (Naticidae), the environmental factor was the freshening of sea water, and the toxic factor used was copper ions. Adding copper to sea water at a concentration of 0.005 mg/l did not reveal any pronounced effect on the development, behavior and growth of larvae in conditions of normal salinity (32‰), however their adaptive potential decreased with a decrease of salinity to 24‰. The results of the present work and experiments carried out previously enabled us to conclude that before assessing any concentration of pollutant as one not affecting marine organisms, it is necessary to investigate not only their development, growth and survival, but also their adaptive capacity relative to the variation of natural environmental parameters, such as even temperature and salinity.

Fatigue data usually display substantial scatter. The goal of this paper is to demonstrate how simulated variation in surface treatment processing parameters and material properties affect the predicted fatigue life (mean and scatter) of a component. This is achieved by applying robust design principles to fatigue life evaluation methods, using shot peening as the representative manufacturing process for this study. Analyzing changes in the appropriate fatigue performance quality characteristic due to variations in the process parameters and material properties will identify levels of the controllable process parameters which maximize the mean fatigue performance and minimize its scatter. The simulation predictions of this study are consistent with past experimental observations which show that compressive residual stress distributions tend to increase mean fatigue life and reduce its scatter for a component. Our results extend these observations by relating the increase in mean life and the reduction in scatter to the controllable manufacturing and design parameters. In addition, the intermediate measure of compressive zone depth is identified as a possible off-line production quality check that relates directly to the component fatigue performance (mean and scatter), as well as an aid to the designer to identify an appropriate surface treatment process. This study serves as an initial step in the development of a generalized methodology that can aid engineers with design for robust fatigue performance for other manufacturing processes.

A research project was undertaken to collect data to study the variability in environmental parameters inside a greenhouse. The specific objectives of the project were to 1) develop the network of open-source sensor nodes, 2) evaluate the performance of the individual sensors, and 3) quantify the spatial variability of environmental parameters within the greenhouse. The sensor system consisted of a sensor node equipped with three temperature and relative humidity sensors, one light-level sensor, one barometric pressure sensor, AA batteries, and a microcontroller board with a built-in radio to transfer the data wirelessly. The sensors were controlled with open-source technology. Twelve sensor nodes were fabricated and placed at different locations in a greenhouse to evaluate variability in sensor location and environmental parameters. Data collected during February 2019 were used to test the sensors. Heatmaps were employed to assess the variability of the measurements. Variability in greenhouse temperature, relative humidity, and light level conditions was identified with the sensor system. Overall, environmental measures based on time of day appeared to be a better grouping mechanism for analysis than sensor location in the greenhouse. Similar patterns were observed between the different sensor manufacturer’s heatmaps for the temperature sensors and relative humidity sensors. This study provided a protocol for developing the inexpensive multi-sensor sensor node and showed that automated measurements obtained with the system could help monitor variation in a greenhouse setting. The costs of the system components fabricated for this study included US$76 for each sensor node and US$55 for the gateway, totaling US$967 for the 12-node study described.

In designing a lightweight torpedo, multiple performance criteria from many disciplines, including structures, acoustics, controls, and hydrodynamics, have to be satisfied in order to maintain a high probability of success for the mission. These criteria could conflict with each other as design requirements, in which case the final design will be the configuration that minimizes conflicts. Performance criteria depend on various design parameters that constitute the configuration of the torpedo and these are usually assigned deterministic values. However, in reality, the parameters would exhibit variations, and thus the design criteria could potentially violate the feasible design space. Therefore, this paper presents a robust torpedo design strategy that provides the designer insight into the safety of the final configuration, subject to variations in design parameters. In this paper a torpedo is modeled using finite elements and its static and dynamic characteristics are analyzed subject to variations in the design parameters structural problem. In this paper, a torpedo is modeled using finite elements and its static and dynamic characteristics are analyzed subject to variations in the design parameters.

The problem of evaluating power cable loading performance subject to variations of the thermal circuit parameters is formulated and solved by a fast sensitivity technique based on the finite element method. The technique provides useful sensitivity information which can be accessed and manipulated by the cable designer or operator to simulate, in a simple and efficient manner, various soil, ambient, loading and boundary variations. The sensitivity technique has been applied to a variety of practical cable systems including direct-buried and pipe-type cables as well as cables in duct banks. The technique reduces significantly the analysis and computations via identifying the important parameters which most affect the ampacity and it simplifies the thermal model by eliminating the low-sensitivity (non-important) parameters. Because the sensitivity values depend on the particular cable system and soil and boundary conditions and can vary significantly from one situation to another, the generalization of the results is not possible. Therefore, the paper describes the sensitivity technique and its direct implementation by illustrating its use for a variety of cable systems.

One critical issue for manufacturing 3D MCM packages is the warpage induced during the process. The effects of several important parameters, including processing conditions, package geometry and materials, are specifically studied on the occurrence of warpage and optimized to reduce the warpage in many previous literatures. However, the design parameter values are not always precisely known but can contain a level of uncertainty to some extent due to, for example manufacturing tolerance. In some case, the design parameters variations can not be neglected. In this paper, the effect of structure geometry tolerance and material property tolerance on package warpage robustness was took into account and analyzed. The robust optimization mathematic model of the 3D packages, considering the uncertainty of the design parameters, was built. And the robust optimization method based on the Monte-carlo simulations and Genetic Algorithm was present to solve the optimization problem above. Firstly, the parametric design finite element model of the specific 3D MCM package was built. Secondly, the statistic distribution of the warpage induced by the design parameters variations was obtained based on the Monte-carlo simulations. Finally, the GA was implemented to optimize the mean value and standard deviation of the warpage. The resulting robust optimization design shows that the robust optimization design is insensitive to variations on design variables within a feasible region.

The design of a digital IC is complicated by the range of timing that must be considered in the design process. Delay variations are commonly associated with power supply variations, temperature and process parameter variations. This paper documents one approach to reducing the delay variations, resulting from environmental conditions and process parameter variations, encountered in digital logic to levels approaching insignificance. This approach does not impact the delay dependency on output loading. >

The quality of a delay test set hinges not only on test patterns and the distribution of the delay defects but on the variations in process parameters as well. Process variations result in the same delay test set displaying differences from die to die in the detection of particular delay defects at the identical circuit node. The application of an identical test set to all devices independent of process variations consequently results in delivering inefficiencies in test time utilization. This paper proposes a delay test technique that adaptively changes the size of the test set based on the position of the device in the process variation space in order to maximize test quality within a given test time.

Min–Max-DEVS modeling and simulation

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65nm gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of response surface methodology (RSM) using design of experiments (DOE) and least squares method (LSM), are employed to generate a for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by at least 6X on a normalized basis, against worst case design

Increasing competition in the global marketplace demands products be adaptable to the changes of functional requirements, operation environments, and technology advancement. Adaptable design can be used for developing adaptable products that can be easily changed, such as reconfigured or upgraded, in the product operation stage. In addition, since the uncertainties in product parameters and environment parameters usually lead to the variations of functional performance, robust design has to be carried out to identify the design whose functional performance is the least sensitive to the variations of product and environment parameters. In this research, a robust adaptable design method is developed to identify the product whose parameter values can be changed in the product operation stage. First, a mathematical model is established to describe the relationships among product functional performances, parameters, and variations of these parameters. Then, an optimization-based design model is developed to achieve the robust adaptable design. A case study has also been developed to demonstrate the effectiveness of the newly developed robust adaptable design method.

Parameter variations are inevitable in any IC process. Process steps such as oxidation, doping, molecular beam epitaxy, etc., are all fundamentally statistical in nature [1]. Design of functioning circuits and systems has traditionally relied heavily on the presumption that the law of large numbers [2] applies and that statistical averaging predominates over random variations – more precisely, that the statistical distributions of important process, geometrical, environmental, and electrical parameters cluster closely about their means. Unfortunately, with feature sizes having shrunk from 90 to 65 nm recently (with further scaling down to 45 and 32 nm predicted by the ITRS roadmap [3]), this assumption is no longer valid – in spite of efforts to control them [4, 5], large variations in process parameters are the norm today. This problem is most severe for circuits that try to use the minimum transistor size (e.g., memory circuits [6] for which chip area is of high priority). With transistors having become extremely small (e.g.: gates are only 10 molecules thick; minority dopants in the channel number in the 10s of atoms), small absolute variations in previous processes have become large relative ones. Lithography-related variability at nanoscales [5], which affect geometrical parameters such as effective length and width, further compound parameter variation problems.

In sub-90 nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated parameters. Variations in the critical process parameters can result in significant fluctuations in the switching speed and leakage power consumption of different transistors in the same chip. In this paper, we study the impact of process variation on issue queues. Due to process variation, issue queues can take variable access latency. In order to work with nonuniform access latency issue queues, by exploiting ready operands of instructions at dispatch time, we propose a process variation aware issue queue design. Experimental results reveal that, for a 64-entry issue queue with half of the entries affected by process variation, our technique recovers most of the lost performance due to process variation and incurs a performance penalty of less than 2% with respect to the performance of issue queues without process variation.