Leakage control for deep-submicron circuits

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

Reduction of leakage current is a grand challenge in logic and analog devices from viewpoints of low power consumption, high resolution, low noise, and so on. As for the P-N junction leakage current, it is reported that the leakage current is caused by several factors such as junction depth [1], shallow trench isolation (STI) stress [2], metal contamination, and crystal defects [3]. In this paper, we focused on the influence of the STI stress on the junction leakage current. To clarify the impact of internal stress in the silicon substrates on the leakage current, a buried P-N junction was used. The buried P-N junction has less sensitivity to SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface states which could dominate the leakage current, and is applied to low leakage devices. We quantified the magnitude of the mechanical stress utilizing Raman spectroscopy and examined the process parameter to reduce the leakage current.

Leakage currents through the gate dielectric of thin film transistors remain a roadblock to the fabrication of organic field-effect transistors (OFETs) on ultrathin dielectrics. We report the first investigation of a self-assembled monolayer (SAM) dipole as an electrostatic barrier to reduce leakage currents in n-channel OFETs fabricated on a minimal, leaky ∼10 nm SiO2 dielectric on highly doped Si. The electric field associated with 1H,1H,2H,2H-perfluoro-octyltriethoxysilane (FOTS) and octyltriethoxysilane (OTS) dipolar chains affixed to the oxide surface of n-Si gave an order of magnitude decrease in gate leakage current and subthreshold leakage and a two order-of-magnitude increase in ON/OFF ratio for a naphthalenetetracarboxylic diimide (NTCDI) transistor. Identically fabricated devices on p-Si showed similarly reduced leakage and improved performance for oxides treated with the larger dipole FOTS monolayer, while OTS devices showed poorer transfer characteristics than those on bare oxide. Comparison of OFETs on both substrates revealed that relative device performance from OTS and FOTS treatments was dictated primarily by the organosilane chain and not the underlying siloxane-substrate bond. This conclusion is supported by the similar threshold voltages (VT) extrapolated for SAM-treated devices, which display positive relative VT shifts for FOTS on either substrate but opposite VT shifts for OTS treatment on n-Si and p-Si. Our results highlight the potential of dipolar SAMs as performance-enhancing layers for marginal quality dielectrics, broadening the material spectrum for low power, ultrathin organic electronics.

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCT's is always "near its cut-off voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC '91 benchmark circuits.

The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures due to parameter variations, and discuss test methodologies to test for process variation induced failures. Next, we describe two different self-repairing techniques?at the circuit level, using adaptive body biasing and at the architecture level, using Built-in-self-test (BIST), redundancy and address remapping. The discussed self-repair mechanisms can improve design yield much beyond what can be achieved using row/column redundancy and error correcting codes (ECC) alone.

This paper has presented doping profile dependent threshold voltage for DGMOSFET using analytical transport model based on Gaussian function. Two dimensional analytical transport model has been derived from Poisson’s equation for symmetrical Double Gate MOSFETs(DGMOSFETs). Threshold voltage rolloff is very important short channel effects(SCEs) for nano structures since it determines turn on/off of MOSFETs. Threshold voltage has to be constant with decrease of channel length, but it shows roll-off due to SCEs. This analytical transport model is used to obtain the dependence of threshold voltage on channel doping profile for DGMOSFET profiles. Also we have analyzed threshold voltage for structure of channel such as channel length and gate oxide thickness.

In recent years, power dissipation in CMOS circuits has grown exponentially due to the fast technology scaling and the increase in complexity. Supply Voltage scaling is an effective technique to reduce dynamic power dissipation due to the non-linear relationship between dynamic power and Vdd. In other words, Vdd can be scaled freely except with limitation for below threshold voltage operation. The dynamic voltage scaling architecture mainly consists of dc-dc power regulator which is customised to produce variability on the Vdd. The implemented architecture can dynamically vary the Vdd from 300 mV to 1.2V, with initial setup time of 1.5 μsec. This paper investigates the effect of DVS on dynamic power dissipation in a Fast Fourier Transform multiplier core. Implementation of DVS on the multiplier blocks has shown 25% of average power reduction. The design was implemented using 0.12μm ST-Microelectronic 6-metal layer CMOS dual- process technology.KeywordsFast Fourier TransformPulse Width ModulatorCharge PumpFast Fourier Transform AlgorithmDynamic Voltage ScalingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

Transformerless Photovoltaic (PV) inverters are gaining popularity compared to their transformer-based counterparts. They are more efficient, cost-effective, and smaller in volume. Despite this, parasitic capacitance causes the common mode current to flow between the PV array and the grid. In addition to losses, leakage current increases electromagnetic interference (EMI) and poses issues to the protection system. Transformerless inverters should therefore be so designed that the leakage current is minimized. Common mode voltage changes (VCM) causes the leakage current. There are a number of PV inverter topologies that have been designed to minimize these variations. This paper discusses H4, H5 and HERIC single-phase PV inverter topologies. Circuit simulations have been used for analysis. HERIC Topology is best one of these since it reduces the leakage current with lowest power loss due to ac bypass instead of usual dc side decoupling. It is a type of resonant converter that operates at high frequencies to achieve efficient power conversion. In this work comparison has been made between topologies for their effectiveness in reducing leakage current. Moreover, its variation with load has been studied, a perspective missed in other studies.

Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.

A device level way to quantitatively assess the influence of Line Edge Roughness (LER) on different fin based structures is considered. We know FinFETs have high drive current and offer better control over leakage and short channel effects. The FinFET device parameters such as On-current, Off-current and threshold voltage are impressionable to structure of FinFET. Performance of the 3D FinFET structures affected by LER. LER is referred to as randomly varied edges or roughness in printed pattern edge. The effect of LER in some cases results in reduction of leakage current, but in some cases it worsened the device parameter. The brunt of random variation sources on the electrical characteristics of the devices are not easy to be discriminated from each other. Random dopant fluctuations (RDF), Metal Gate Granularity (MGG) and Line Edge Roughness (LER) are the severe random variations which enforce restraints on the FinFET. Here an investigation on the effect of LER on the threshold voltage and On-current of SOI, Bulk and GAA FinFET is proposed. A comparative study on different structures is also presented. All simulations are carried out in Silvaco Atlas TCAD.

A general concern in VLSI design is power efficiency. It is indeed very obvious that battery operated equipment, such as handheld cellular phones, laptop computers etc. impose stringent limits on the acceptable power dissipation. The power dissipation of CMOS circuits is determined at different levels. On the system/architecture level, pipelining, replication, retiming, and bit-serial operation can result in power savings [1]. Moreover, new technologies with smaller feature sizes and lower supply voltages contribute to lowering power dissipation. In this paper author used an extra circuitry that is demultiplexer and an ALU design to explain the concept of reducing power consumption. The technique that author has used in this paper is also applicable for other designs like processor or any other real time process designing.

The rise in renewable energy has increased the use of DC/AC converters, which transform the direct current to alternating current. These devices, generally called inverters, are mainly used as an interface between clean energy and the grid. It is estimated that 21% of the global electricity generation capacity from renewable sources is supplied by photovoltaic systems. In these systems, a transformer to ensure grid isolation is used. Nevertheless, the transformer makes the system expensive, heavy, bulky and reduces its efficiency. Therefore, transformerless schemes are used to eliminate the mentioned disadvantages. One of the main drawbacks of transformerless topologies is the presence of a leakage current between the physical earth of the grid and the parasitic capacitances of the photovoltaic module terminals. The leakage current depends on the value of the parasitic capacitances of the panel and the common-mode voltage. At the same time, the common-mode voltage depends on the modulation strategy used. Therefore, by the manipulation of the modulation technique, is accomplished a decrease in the leakage current. However, the connection standards for photovoltaic inverters establish a maximum total harmonic distortion of 5%. In this paper an analysis of the common-mode voltage and its influence on the value of the leakage current is described. The main topologies and strategies used to reduce the leakage current in transformerless schemes are summarized, highlighting advantages and disadvantages and establishing points of comparison with similar topologies. A comparative table with the most important aspects of each converter is shown based on number of components, modes of operation, type of modulation strategy used, and the leakage current value obtained. It is important to mention that analyzed topologies present a variation of the leakage current between 0 to 180 mA. Finally, the trends, problems, and researches on transformerless grid-connected PV systems are discussed.

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.