An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits

Demand for low power circuits is increasing and an easy way to meet low power requirement is to scale down the supply voltage. When the power supply is less than the threshold voltage of the transistors, the circuit is said to be operating in the subthreshold region. This work presents a novel 9T subthreshold SRAM cell. Some important features of the proposed design are employment of single-ended write scheme and differential sensing scheme for read operation. Another important highlight of the proposed design is the use of stack transistor in the left part of the cross-coupled inverter. Stacking leads to substantial reduction in leakage current. The proposed design has been compared to the previously proposed conventional 9T SRAM cell. It is observed that the proposed design shows 1.95× improvement in read access time and 1.94× improvement in leakage current as compared to the conventional 9T SRAM cell at a supply voltage of 300 mV. Also, there is 5.5% improvement in hold power and 1.67× improvement in hold power variability at VDD = 300 mV. The simulation tool used for estimation of the parameters is Synopsys' HSPICE.

Leakage currents through the gate dielectric of thin film transistors remain a roadblock to the fabrication of organic field-effect transistors (OFETs) on ultrathin dielectrics. We report the first investigation of a self-assembled monolayer (SAM) dipole as an electrostatic barrier to reduce leakage currents in n-channel OFETs fabricated on a minimal, leaky ∼10 nm SiO2 dielectric on highly doped Si. The electric field associated with 1H,1H,2H,2H-perfluoro-octyltriethoxysilane (FOTS) and octyltriethoxysilane (OTS) dipolar chains affixed to the oxide surface of n-Si gave an order of magnitude decrease in gate leakage current and subthreshold leakage and a two order-of-magnitude increase in ON/OFF ratio for a naphthalenetetracarboxylic diimide (NTCDI) transistor. Identically fabricated devices on p-Si showed similarly reduced leakage and improved performance for oxides treated with the larger dipole FOTS monolayer, while OTS devices showed poorer transfer characteristics than those on bare oxide. Comparison of OFETs on both substrates revealed that relative device performance from OTS and FOTS treatments was dictated primarily by the organosilane chain and not the underlying siloxane-substrate bond. This conclusion is supported by the similar threshold voltages (VT) extrapolated for SAM-treated devices, which display positive relative VT shifts for FOTS on either substrate but opposite VT shifts for OTS treatment on n-Si and p-Si. Our results highlight the potential of dipolar SAMs as performance-enhancing layers for marginal quality dielectrics, broadening the material spectrum for low power, ultrathin organic electronics.

Reduction of leakage current is a grand challenge in logic and analog devices from viewpoints of low power consumption, high resolution, low noise, and so on. As for the P-N junction leakage current, it is reported that the leakage current is caused by several factors such as junction depth [1], shallow trench isolation (STI) stress [2], metal contamination, and crystal defects [3]. In this paper, we focused on the influence of the STI stress on the junction leakage current. To clarify the impact of internal stress in the silicon substrates on the leakage current, a buried P-N junction was used. The buried P-N junction has less sensitivity to SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface states which could dominate the leakage current, and is applied to low leakage devices. We quantified the magnitude of the mechanical stress utilizing Raman spectroscopy and examined the process parameter to reduce the leakage current.

Transformerless Photovoltaic (PV) inverters are gaining popularity compared to their transformer-based counterparts. They are more efficient, cost-effective, and smaller in volume. Despite this, parasitic capacitance causes the common mode current to flow between the PV array and the grid. In addition to losses, leakage current increases electromagnetic interference (EMI) and poses issues to the protection system. Transformerless inverters should therefore be so designed that the leakage current is minimized. Common mode voltage changes (VCM) causes the leakage current. There are a number of PV inverter topologies that have been designed to minimize these variations. This paper discusses H4, H5 and HERIC single-phase PV inverter topologies. Circuit simulations have been used for analysis. HERIC Topology is best one of these since it reduces the leakage current with lowest power loss due to ac bypass instead of usual dc side decoupling. It is a type of resonant converter that operates at high frequencies to achieve efficient power conversion. In this work comparison has been made between topologies for their effectiveness in reducing leakage current. Moreover, its variation with load has been studied, a perspective missed in other studies.

The rise in renewable energy has increased the use of DC/AC converters, which transform the direct current to alternating current. These devices, generally called inverters, are mainly used as an interface between clean energy and the grid. It is estimated that 21% of the global electricity generation capacity from renewable sources is supplied by photovoltaic systems. In these systems, a transformer to ensure grid isolation is used. Nevertheless, the transformer makes the system expensive, heavy, bulky and reduces its efficiency. Therefore, transformerless schemes are used to eliminate the mentioned disadvantages. One of the main drawbacks of transformerless topologies is the presence of a leakage current between the physical earth of the grid and the parasitic capacitances of the photovoltaic module terminals. The leakage current depends on the value of the parasitic capacitances of the panel and the common-mode voltage. At the same time, the common-mode voltage depends on the modulation strategy used. Therefore, by the manipulation of the modulation technique, is accomplished a decrease in the leakage current. However, the connection standards for photovoltaic inverters establish a maximum total harmonic distortion of 5%. In this paper an analysis of the common-mode voltage and its influence on the value of the leakage current is described. The main topologies and strategies used to reduce the leakage current in transformerless schemes are summarized, highlighting advantages and disadvantages and establishing points of comparison with similar topologies. A comparative table with the most important aspects of each converter is shown based on number of components, modes of operation, type of modulation strategy used, and the leakage current value obtained. It is important to mention that analyzed topologies present a variation of the leakage current between 0 to 180 mA. Finally, the trends, problems, and researches on transformerless grid-connected PV systems are discussed.

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.

A new model is proposed for the AC-stress-induced leakage current in flash EEPROM tunnel oxides. This model is based on tunneling trap sites generated (increased leakage) during the on-time of a stress pulse and deactivated (decreased leakage) during the off-time. We have characterized this neutralization effect and its role in the reduction of the AC-stress-induced leakage current. Using the model developed in this work, the optimum programming waveform to minimize leakage current is a long single pulse with the reverse polarity bias during the long off time in the case that the total on and off time is constant. This reduction in stress-induced leakage current is critical to minimizing read disturb errors in flash EEPROMs.

A new model is proposed for the AC-stress-induced leakage current in flash EEPROM tunnel oxides. This model is based on tunneling trap sites generated (increased leakage) during the on-time of a stress pulse and deactivated (decreased leakage) during the off-time. We have characterized this neutralization effect and its role in the reduction of the AC-stress-induced leakage current. Using the model developed in this work, the optimum programming waveform to minimize leakage current is a long single pulse with the reverse polarity bias during the long off time in the case that the total on and off time is constant. This reduction in stress-induced leakage current is critical to minimizing read disturb errors in flash EEPROMs.

Scaling CMOS: Finding the gate stack with the lowest leakage current

Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are linearized and incorporated into an exact (optimal) integer linear programming (ILP) model, called virtual-gate ILP, which analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also proposed, which has several advantages: it is faster, its accuracy can be quickly estimated, and tradeoffs between runtime and optimality can easily be made. Furthermore, the MLP model also provides a way to estimate a lower bound on circuit leakage current. The proposed methods are used to generate an extensive set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum. In addition, the lower bound estimated by the MLP model is also within a few percent of the optimal value

In this letter, we find an efficient way to suppress UV damage on the characteristics of polysilicon thin-film transistors (TFTs) during hydrogenation for high density TFT SRAM. Polysilicon TFT can be free from UV damage during hydrogenation if the channel region is shielded by a metal line of the same width as channel. After hydrogenation, the metal shielded TFT shows an excellent subthreshold swing of 112 mV/dec, and the leakage current can be as low as 20 fA while the unshielded TFT shows a subthreshold swing of 220 mV/dec and a leakage current of 0.33 pA. This gives almost 200% improvement in subthreshold swing and one order of magnitude reduction in leakage current.

Pulse recovery time in semiconducting devices depends strongly on minority carrier lifetime, bandgap-type-dependent recombination, impurity concentration, and subband placement. In indirect bandgap solids, such as silicon, it is dominated by Shockley–Reed–Hall (SRH) recombination via trap-based recombination centers yielding slow recombination. The sluggish recombination then limits the pulse repetition rate and consequently the average power to a load. For decades, fabrication and irradiation techniques, such as Au- and Pt-diffusion, and energized electron-, proton-, and alpha particle-beam bombardment have been used to adjust minority carrier lifetime in silicon. These techniques generate shallow- and/or deep-level lattice defects to promote/retard trap-assisted SRH recombination. Despite investigating the characteristics of the generated defects on target material, the prior-art falls short in comprehensively addressing their effects on device-level architecture, specifically photoconductive switching devices. In this work, the effect of proton irradiation-induced localized crystal defect clusters on minority carrier lifetime in silicon photoconductive semiconductor switches is investigated when bombarded with 2.5–5 MeV beam energies with fluences between 9 × 1012–11 × 1013 cm−2 at room temperature. Photo-illuminated recovery characteristics for proton-beam (p-beam) irradiated device models with three distinct defect profiles have been studied using Silvaco TCAD and results have been compared with the electron-beam (e-beam) irradiation model with three different distinct defect profiles. At 30× lower defect density, recovery time trends in the p-beam irradiated device model were seen to be on the same order of magnitude as the e-beam irradiated model. At similar defect densities (1 × 1016 cm−3), the profile with a uniformly distributed bulk defect profile performed 10× better from a recovery time viewpoint compared with the e-beam irradiation. Furthermore, three orders of magnitude reduction in leakage currents were noticed in p-beam irradiated models.

High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techniques. At the process level, leakage reduction can be achieved by controlling the dimensions (length, oxide thickness, junction depth, etc) and doping profile in transistors. At the circuit level, threshold voltage and leakage current of transistors can be effectively controlled by controlling the voltages of different device terminals (drain, source, gate, and body (substrate)).

Common-mode (CM) leakage current is an important symptom in cable insulation monitoring. However, traditional current sensors suffer from low accuracy when extracting small-amplitude leakage current from large-amplitude load current. This article proposes an open-type high-precision CM leakage current sensor model to achieve online monitoring of CM leakage current in cables. Through symmetrically arranging four tunnel magnetoresistance (TMR) chips outside the shielding ring and averaging their output results, the load current component can be eliminated to the lowest level and the CM leakage current component can be retained. This open-type structure resolves the installation challenges associated with closed-type shielding ring in long cables, and four symmetrically arranged TMR Chips can further reduce the error introduced by the open structure, which enables the extraction of 20 mA CM leakage current with relative error less than 5%, even in the presence of 200 A load current.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO