An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space

It is widely believed that any true (or sensitizable) critical path of length /spl ges/2 T must be speeded up in order for a circuit to have a delay <T. I demonstrate that this notion is pessimistic. Many true paths can never affect the delay of the circuit-whenever such a path propagates a signal, some other path that is at least as long also propagates a signal. The theory for a new classification of paths based on the impact on the circuit delay is presented and conditions are given under which a path (or a set of paths) must be speeded up in order to improve the circuit delay. The conditions for the categorization are independent of the delays in the circuit and are valid for all delay assignments. This work indicates that the widely employed notions of true and false paths may be misleading both for timing optimization and delay analysis of logic circuits.

In recent years, there has been a lot of research into statistical static timing analysis (SSTA) to compute the critical path delay of a circuit under timing variation. In order to compute the true critical path delay, however, false paths that cannot be sensitized by any input vector must be identified first. Since SSTA is unable to capture the dynamic timing behavior of a circuit, it is completely blind to false paths, and thus it overestimates the circuit timing. In this paper, we propose a new concept of timing analysis approach called statistical dynamic timing analysis (SDTA), which is able to precisely express the statistical behavior of dynamic transitions at the output of gate into a compact form and to directly evaluate and propagate the expressions throughout the circuit, by which the false paths can be cleaned effectively. In addition, to be practical, we propose a couple of techniques that enable a fast computation of the SDTA. We tested the proposed approach on ISCAS benchmarks and carry skip adders under timing variation to show its accuracy in computing the distribution of the true critical path delay of a circuit. In summary, compared to the previous approach of false path-aware statistical timing analysis, our timing analysis technique is able to reduce the accuracy error in the mean and standard deviation of true critical path delay distribution from 9.8% to 1.9% and from 29.4% to -3.4%, respectively.

The extreme complexity of digital systems enabled by nanometer-scale implementation technologies comes along with strengthened design requirements that are difficult to achieve with the conventional techniques. Over-designing beyond the minimal required guarantees may have negative impacts on the overall system’s cost. In this paper we focus on the task of timing-critical logic paths identification in digital systems that has many applications in design and test field, like verifying the timing constraints of designs, estimating critical delays, Simulating path delay faults and reliability analysis such as ageing. The contribution is a new scalable simulation-based hierarchical search method for application-specific online-viable true critical paths identification in sequential circuits. The approach is motivated by the concept of mixed-critical systems, but it can be applied for any type of digital system. We propose to represent the circuits hierarchically at the level of higher level submodules using t e theory of Structurally Synthesized BDDs (SSBDD). The search space is limited by the application-specific context that enables accurate results even for complex sequential circuits. Experimental results demonstrate efficiency of the proposed approach, and considerable reduction of the length of critical paths if the application-specific constraints are taken into account.

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.

We propose a scalable efficient parameterized block-based statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. As a preprocessing step, we employ an independent component analysis to transform the set of correlated non-Gaussian parameters to a basis set of parameters that are statistically independent. Given the moments of the variational parameters, we use a Pade acute-approximation-based moment-matching scheme to generate the distributions of the random variables representing the signal arrival times and preserve correlation information by propagating arrival times in a canonical form. Our SSTA procedure is able to generate the circuit delay distributions with reasonably small prediction errors. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99%, 2.05%, 2.33%, and 2.36%, respectively, in the mean, standard deviation, and 5% and 95% quantile points of the circuit delay. Experimental results show that our procedure can handle as many as 256 correlated non-Gaussian variables in about 5 min of runtime. For a circuit with |G| gates and a layout with g spatial correlation grids, the complexity of our approach is O(g|G|) .

With the ever decreasing transistor feature size in recent years, process variation has become a serious challenge in digital system design, mainly due to the undesirable timing uncertainty it introduces in circuits. This variation in the size of circuit components changes the logic and wire delays that in turn, may result in delay faults or clock degradation. In this paper, we propose to use the emerging approximate computing technique to tackle the process variation problem in new technology points. In this method, functional units (sub-blocks) along critical paths are replaced with a faster approximate version to guarantee timing closure in presence of process variation. Approximation not only applies to critical path sub-blocks but also to the paths with the length close enough to critical path length that variation can potentially increase their delay over the critical path. Evaluation results under several benchmarks show that this method can give a required safety margin against delay faults, while its side-effect, i.e. accuracy loss, is still low and acceptable.

We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tail of the delay distribution. A ¿naive¿ MCMC approach is inadequate for SSTA. Several modifications and enhancements, presented in this paper, enable application of MCMC to SSTA. Moreover, such an approach overcomes inherent limitations of techniques such as importance sampling and Quasi-Monte Carlo. Our results on open source designs, with an independent delay variation model, demonstrate that our technique can obtain more than an order of magnitude improvement in computation time over simple Monte Carlo, given an estimation accuracy target at a point in the tail. Our approach works by providing a large number of samples in the region of interest. Open problems include extension of algorithm applicability to a broader class of synthesis conditions, and handling of correlated delay variations. In a broader context, this work aims to show that MCMC and associated techniques can be useful in rare event analyses related to circuits, particularly for high-dimensional problems.

This paper introduces a novel compact implicit model for a probabilistic set of waveforms (PSoW) which arise as representations for uncertain signal waveforms in Statistical Static Timing Analysis (SSTA). In traditional SSTA tools, signals are just represented as (distributions of) arrival time and slew. In our approach, to increase accuracy, PSoW's are used instead. However, to represent PSoW's explicitly, a very large amount of data is necessary, which can be problematic. To solve this problem, a compact implicit model is introduced, which can be characterized with just a handful of parameters. The results obtained show that the implicit model can generate real-life PSoW's with high accuracy.

In this paper, we explore the implementation of Monte Carlo based statistical static timing analysis (SSTA) on a Graphics Processing Unit (GPU). SSTA via Monte Carlo simulations is a computationally expensive, but important step required to achieve design timing closure. It provides an accurate estimate of delay variations and their impact on design yield. The large number of threads that can be computed in parallel on a GPU suggests a natural fit for the problem of Monte Carlo based SSTA to the GPU platform. Our implementation performs multiple delay simulations at a single gate in parallel. A parallel implementation of the Mersenne Twister pseudo-random number generator on the GPU, followed by Box-Muller transformations (also implemented on the GPU) is used for generating gate delay numbers from a normal distribution. The μ and σ of the pin-to-output delay distributions for all inputs and for every gate, are obtained using a memory lookup, which benefits from the large memory bandwidth of the GPU. Threads which execute in parallel have no data/control dependencies on each other. All threads compute identical instructions, but on different data, as required by the Single Instruction Multiple Data (SIMD) programming semantics of the GPU. Our approach is implemented on a NVIDIA GeForce GTX 8800 GPU card. Our results indicate that our approach can obtain an average speedup of about 260x as compared to a serial CPU implementation. With the recently announced quad 8800 GPU cards, we estimate that our approach would attain a speedup of over 785x. The correctness of the Monte Carlo based SSTA implemented on a GPU has been verified by comparing its results with a CPU based implementation.

Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

Existing statistical static timing analysis (SSTA) techniques suffer from limited modeling capability by using a linear delay model with Gaussian distribution, or have scalability problems due to expensive operations involved to handle non-Gaussian variation sources or non-linear delays. To overcome these limitations, we propose a novel SSTA technique to handle both nonlinear delay dependency and non- Gaussian variation sources simultaneously. We develop efficient algorithms to perform all statistical atomic operations (such as max and add) efficiently via either closed- form formulas or one-dimensional lookup tables. The resulting timing quantity provably preserves the correlation with variation sources to the third-order. We prove that the complexity of our algorithm is linear in both variation sources and circuit sizes, hence our algorithm scales well for large designs. Compared to Monte Carlo simulation for non-Gaussian variation sources and nonlinear delay models, our approach predicts all timing characteristics of circuit delay with less than 2% error.

This work is aimed at the development of a path-based approach to Statistical Static Timing Analysis. Timing Analysis is an absolutely essential step in the verification of Very Large Scale Integration (VLSI) designs. We propose a novel analytical methodology for the fast calculations of VLSI delay. The problem is stated in such a way that becomes equivalent to finding the maximum of a large set of correlated random variables (RVs). For this purpose, a corresponding extension of extreme value theory of weakly-correlated RVs is developed. Results of simulations showing a comparison of our approach with Monte Carlo simulations are presented. Possible applications, extensions of our methodology and future steps are discussed.

Recent technology advancements have put a lot of emphasis on the optimization of three main aspects - speed, power, and area. The speed of a digital circuit is always dependent upon clock frequency. The clock frequency of a digital circuit is predominantly influenced by the computational cost of the critical path. The critical path of the digital circuits that contain combinational and sequential elements like FIR, IIR Filters, Multipliers, Adders, Digital Signal Processors (DSPs), etc. can be optimized by rearranging the delay(s) of the critical path, which eventually reduces computational cost without trading with the functionality and input-output relation of the circuit. The term ‘Retiming’ is used to describe the technique of reorganizing the storage elements (registers) in a digital circuit while maintaining its functionality. Currently, python is becoming a choice for a large community of software developers, in the VLSI domain also it is gaining popularity as a scripting language. In this article, the python implementation of the retiming technique is proposed, which takes a Data Flow Graph (DFG) of a non-retimed Digital Circuit as an input to generate the optimized DFG with less critical path delay by Brute Force search, thereby improving overall performance.

An accurate prediction of circuit delay distribution is essential to verify the timing closure of digital circuits and to estimate the parametric yield. In the presence of process variations, the most accurate technique for circuit delay prediction is using Monte Carlo simulations. However, to get an accurate estimate, a large number of Monte Carlo simulations are required which is infeasible in the case of large circuits. Although statistical timing analysis techniques are widely used to predict the circuit delay distribution in a reasonable run time, the standard deviation of circuit delay is often inaccurate. In this work, an efficient technique for circuit delay prediction using limited number of Monte Carlo simulations is proposed. This is done using the concept of Bayesian inference with the results from statistical timing analysis as the prior information. The results indicate that combining statistical timing analysis along with limited number of Monte Carlo simulations increases the accuracy of prediction of circuit delay variance. The number of Monte Carlo simulations can be decided based on the accuracy requirements or run time constraints.