An Efficient FFT Processor for DAB Receiver Using Circuit-Sharing Pipeline Design

In this paper, a "Circuit-sharing scheme" is proposed to design a reduced chipset for DAB (digital audio broadcasting) receiver, involved the fast Fourier transform (FFT) circuit in the orthogonal frequency division multiplexing (OFDM) and IMDCT (inverse modified discrete cosine transform) synthesis filter in the audio decoder Comparing to the existent method, it can achieve a highly integrated, low power and small size DAB receiver. We implement the IMDCT synthesis filter of MPEG audio decoder and the 2048-point complex FFT by a single processing element with pipeline structure. Simulations demonstrate that the proposed circuit sharing can reduce the chipset area and meet the specification of DAB. The gate count is about 6692 excluding the 2048/spl times/16 RAM and 512/spl times/32 ROM.

This thesis presents a green design of fast recursive discrete Fourier transform (RDFT) architecture. The advantages of the proposed design include high-throughput, power-efficient, memory-free and more reconfigurable. This thesis also discuss the issue of applying this RDFT design to Modified Discrete Cosine Transform (MDCT) and Inverse Modified Discrete Cosine Transform (IMDCT), which results in an improvement of hardware-sharing and achieves lower-cost. To improve the lack-of-efficiency problem in traditional RDFT architecture, the 2-D architecture algorithm is used in our design. Compared with the latest RDFT architecture proposed by Lai et al, 49.53% reduction of the overall clock cycles is presented in our design; and the computational amount of multiplication and addition presented are reduced to 53.60% and 53.03% of Lai’s design. In addition, the proposed architecture holds four times of DTPT (Data Throughput per Transformation, DTPT) than the traditional architecture; which achieves our goal of presenting a low complexity and low power-cost design. Furthermore, this architecture is applied on Digital Radio Mondiale (DRM) system in our design. Not only DFT computation(288、256、176、112 point) but MPGE-4 HE-AAC techniques are applied on DRM audio coding(1920、240 point). Therefore, to design a common architecture of DFT and IMDCT becomes an important issue for portable DRM receiver. This system is used to examine the performance of the RDFT architecture which we proposed in the front text as well as to discuss other architectures in this article. Moreover, this RDFT processor is implemented by using TSMC 0.18µm 1P6M CMOS technology. The core size is 0.84x0.84mm2 and the power consummation is 14.6mW@25MHz. To conclude, the proposed design would be more efficient and more suitable for DRM applications than previous works.

The implementation of advanced channel receivers using low-end, though specialised instruction set, media processors is very attractive because of design productivity and cost efficiency reasons. However, achieving real-time using these platforms is not a trivial task. In this paper, we illustrate the application of our data transfer and storage exploration methodology for the implementation of a digital audio broadcast (DAB) channel receiver in real-time using a low-end Trimedia TM1000 processor. We show how the platform independent data transfer and storage related bottlenecks are first eliminated, so in a second phase, the resulting application source code can be transformed to optimally exploit the available memory hierarchy while efficiently using the sub-word-level acceleration capabilities provided by Trimedia's instruction set architecture. These optimisations have brought sufficient speed-up improvements so as to allow real-time execution of the decoder, obtaining about a factor 8 speed-up when compared to a reference functional implementation of the DAB standard.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are the key computation block in Orthogonal Frequency Division Multiplexing (OFDM) system. They dominate most of the areas and power dissipation in implementation therefore efficient low-power and high-throughput implementation of FFT processor is essential for successful deployment of OFDM based system. High-throughput and Low-power 128-point FFT Processor is designed using Radix-25 algorithm to reduce computation complexity and the feedforward pipeline architecture [called Multipath Delay Commutator (MDC)] with four data path for providing higher throughput. This architecture is more hardware-efficient than Multipath parallel feedback (MDF) design, which makes them attractive for the computation of FFT in most demanding applications. The proposed FFT processor uses improved Digit slice multiplier for complex multiplication. This proposed FFT processor is designed using Verilog and implemented using 180 nm CMOS Technology with supply voltage of 1.8v. The result shows significant reduction in power consumption in comparison with existing design and increasing throughput with area trade off.

An OFDMA based channel access scheme is proposed for dynamic spectrum access to utilize frequency spectrum efficiently. Though the OFDMA based scheme is flexible enough to change the bandwidth and channel of the transmitted signals, the OFDMA signal has large PAPR (Peak to Average Power Ratio). In addition, if the OFDMA receiver does not use a filter to extract sub-carriers before FFT (Fast Fourier Transform) processing, the designated sub-carriers suffer large interference from the adjacent channel signals in the FFT processing on the receiving side. To solve the problems such as PAPR and adjacent channel interference encountered in the OFDMA based scheme, this paper proposes a novel dynamic channel access scheme using overlap FFT filter-bank based on single carrier modulation. It also shows performance evaluation results of the proposed scheme by computer simulation.

Moving Pictures Expert Group (MPEG) audio Layer III is the most advanced standard for digital audio compression. The high coding gain of the standard is due to its time to frequency mapping section, which is also the most compute intensive part of the audio coder. It has been shown in the literature that the Discrete Cosine Transform (DCT) proposed in the standard for the filterbank section could be implemented using the Fast Hartley Transform (FHT) in order to reduce the amount of computations and memory accesses. In this paper, an efficient approach is proposed for implementing the synthesis filterbank of the MPEG audio Layer III. The approach is based on a mixed radix FHT for implementing the Inverse Modified Discrete Cosine Transform (IMDCT) section and a radix-2 FHT for the subband decoding section. A high throughput pipeline VLSI architecture is designed for implementing the proposed approach. The architecture has been simulated and verified using the Cadence Verilog-XL simulator.

In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements. A 1k-32k flexible FFT core is implemented in the Altera FPGA, results show that our proposed scheme is suitable for applications where flexible large size FFT processor is needed such as digital video broadcasting, wireless networks etc.

Fast Fourier Transform (FFT) processors, having a significant impact on the performance of communication systems, have been a hot topic of research for many years. FFT function consists of consecutive multiply-add operations over complex numbers, dubbed as butterfly units. Use of redundant number systems is a way of increasing the speed of FFT coprocessors. It eliminates carry-propagation and hence permits latency reduction of each stage of the pipelined FFT architecture. This paper proposes a high-speed FFT processor using the devised fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on Binary-Signed-Digit (BSD) representation. Three-operand BSD adder and BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and in the parallel BSD multiplier, so as to improve the speed of the FDPA unit. Moreover, modified-booth encoding is used to accelerate the BSD multiplier. Synthesis results show that the proposed design is about two times faster than the best previous work; but at cost of more area/power consumption.

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically (log 2 N) as the transform length (N) increases, the number of required registers (or, memories) increases linearly. In large transform length FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined integer mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 34.7% area reduction and 33.4% power reduction compared with conventional IFFT designs.

In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over Digital Audio Broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a Personal Computer via an USB port. We have implemented the system on an FPGA with an embedded RISC processor. We also describe the tools whose development was needed to ease the IP extractor development and to test the functionality of the system. Finally the results of our tests with two applications of IP data transmission over DAB networks -data carousels and video streaming- are presented.

There exist Fast Fourier transform (FFT) algorithms, called dimensionless FFTs, that work independent of dimension. These algorithms can be configured to compute different dimensional DFTs simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows us to design an FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this paper we design a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow, and show how to map different dimensionless FFTs onto this hardware design. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. Using a performance model we search for the optimal algorithm for the family of processors we considered. The resulting algorithm and corresponding hardware design was implemented using FPGA.

This paper presents fully parallel fast Fourier transform (FFT) processor for coherent optical OFDM system. It has a length of 256. For processing of 100 Gb/s throughput it has parallel input and output structure. FFT processor has 32 radix-16 processor with trivial multiplication and consists of an array structure in parallel arithmetic processing. We designed and implemented the proposed FFT processor using Xilinx FPGA XCVU190. The result shows 205,530 LUTs and the maximum throughput is 46.592 Giga-Samples/sec.

This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.