Circuit-sharing design between FFT and IMDCT with pipeline structure for DAB receiver

With the upcoming fourth generation wireless systems and convergence of multiple radio standards into a single terminal, building blocks are needed that can be configured for computing various algorithms used in different standards. Given these trends and requirements, in our previous paper we successfully proposed a circuit-sharing design for the DAB receiver to integrate the FFT (fast Fourier transform) and IMDCT (inverse modified discrete cosine transform) operations into the same functional circuit. The proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. To further improve the efficiency of our previous work, this investigation proposes another alternative design named the circuit-sharing pipeline design (CSPD) using a single processor with a pipeline scheme to combine two functions, FFT and IMDCT, into the same circuit. The proposed method reduces the required chip area and cost of DAB receivers. Analyzing the existing relationship among IMDCT, DCT (discrete cosine transform) and FFT, the IMDCT function can be replaced using a FFT function. Therefore, it is not necessary to design an extra circuit for IMDCT. The arithmetic unit in the FFT processor can be significantly reduced due to employing the pipeline scheme. Consequently, the circuit redundancies in the IMDCT and FFT functions can be easily eliminated to allow exploitation of the decreased chip area. Results of this study demonstrate that the proposed design can provide advantages such as low gate count and small memory size in the DAB (digital audio broadcasting) receiver.

The implementation of advanced channel receivers using low-end, though specialised instruction set, media processors is very attractive because of design productivity and cost efficiency reasons. However, achieving real-time using these platforms is not a trivial task. In this paper, we illustrate the application of our data transfer and storage exploration methodology for the implementation of a digital audio broadcast (DAB) channel receiver in real-time using a low-end Trimedia TM1000 processor. We show how the platform independent data transfer and storage related bottlenecks are first eliminated, so in a second phase, the resulting application source code can be transformed to optimally exploit the available memory hierarchy while efficiently using the sub-word-level acceleration capabilities provided by Trimedia's instruction set architecture. These optimisations have brought sufficient speed-up improvements so as to allow real-time execution of the decoder, obtaining about a factor 8 speed-up when compared to a reference functional implementation of the DAB standard.

System-on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platforms such as FPGA, CPLD, and PLD are now being used for designing and implementing SoC due to their low cost, high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver have been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX and LTE etc. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio broadcasting, Asynchronous Digital Subscriber Line (ADSL) and High bit-rate Digital Subscriber Line (HDSL) systems. In OFDM, two algorithms digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8-point IFFT/FFT Decimation-In-Frequency (DIF) with radix-2 algorithm has been analyzed and incorporated in the design. The design has been simulated on the FPGA platform with Altera's Quartus II simulator. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.

This thesis presents a green design of fast recursive discrete Fourier transform (RDFT) architecture. The advantages of the proposed design include high-throughput, power-efficient, memory-free and more reconfigurable. This thesis also discuss the issue of applying this RDFT design to Modified Discrete Cosine Transform (MDCT) and Inverse Modified Discrete Cosine Transform (IMDCT), which results in an improvement of hardware-sharing and achieves lower-cost. To improve the lack-of-efficiency problem in traditional RDFT architecture, the 2-D architecture algorithm is used in our design. Compared with the latest RDFT architecture proposed by Lai et al, 49.53% reduction of the overall clock cycles is presented in our design; and the computational amount of multiplication and addition presented are reduced to 53.60% and 53.03% of Lai’s design. In addition, the proposed architecture holds four times of DTPT (Data Throughput per Transformation, DTPT) than the traditional architecture; which achieves our goal of presenting a low complexity and low power-cost design. Furthermore, this architecture is applied on Digital Radio Mondiale (DRM) system in our design. Not only DFT computation(288、256、176、112 point) but MPGE-4 HE-AAC techniques are applied on DRM audio coding(1920、240 point). Therefore, to design a common architecture of DFT and IMDCT becomes an important issue for portable DRM receiver. This system is used to examine the performance of the RDFT architecture which we proposed in the front text as well as to discuss other architectures in this article. Moreover, this RDFT processor is implemented by using TSMC 0.18µm 1P6M CMOS technology. The core size is 0.84x0.84mm2 and the power consummation is 14.6mW@25MHz. To conclude, the proposed design would be more efficient and more suitable for DRM applications than previous works.

Fast Fourier Transform (FFT) processing is one of the key procedures in popular Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor for OFDM applications is presented. The processor can be used in various OFDM-based communication systems, such as worldwide interoperability for Microwave access (Wi-Max), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVBT). We adopt single-path delay feedback architecture. To eliminate the Read Only Memories (ROM’s) used to store the twiddle factors, this proposed architecture applies a reconfigurable complex multiplier to achieve a ROM-less FFT/IFFT processor and to reduce the truncation error we adopt the fixed width modified booth multiplier. The three Processing Elements (PE’s), Delay-Line (DL) buffers are used for computing IFFT. Thus we consume the low power, lower hardware cost, and high efficiency and reduced chip size.

Orthogonal Frequency Division Multiplexing (OFDM) is one of the promising contendents in the race of very high data rate delivery, for 4G wireless systems. The conventional OFDM systems, so far deployed make use of Fast Fourier Transform (FFT) as their basic building block. Besides the numerous advantages, the restriction over the data rate imposed by the FFT in the form of cyclic prefix may be intolerable for the next generation OFDM systems. So, researches are on the way to replace FFT with a more suitable transform which is redundant free. DWT OFDM is one such system in which FFT in the conventional OFDM is replaced with Discrete Wavelet Transform (DWT). Using simulations, already it has been established that in ideal conditions, the performance of DWT OFDM is better than that of FFT OFDM. As phase noise can be considered as the major RF impairment and one of the leading performance limiting factors of the wireless systems, this paper analyses the Bit Error Rate (BER) performance of the DWT OFDM in presence of phase noise. BER performances of both DWT OFDM and FFT OFDM are analysed and compared in presence of phase noise. For this, Matlab Simulink model have been developed for both types of OFDM, and simulation is carried over in presence of phase noise for different modulation schemes. In all cases the BER performances of DWT OFDM is found to be fairly ahead that of FFT OFDM.

Orthogonal frequency division multiplexing (OFDM) is a block transmission technique with bandwidth efficient signalling scheme for wideband digital communications. In OFDM the spectrum of the individual carriers mutually overlaps. Nevertheless, the OFDM carriers exhibit orthogonality on a symbol interval if they are spaced in frequency exactly at the reciprocal of the symbol interval, which can be accomplished by utilizing the discrete time Fourier transform (DFT). In the baseband, complex-valued data symbols modulate a large number of tightly grouped carrier waveforms. The transmitted OFDM signal multiplexes several low-rate data streams each data stream is associated with a given subcarrier. The main advantage of this concept in a radio environment is that each of the data streams experiences an almost flat fading channel. In slowly fading channels, the inter-symbol interference (ISI) and inter-carrier interference (ICI) within an OFDM symbol can be avoided with a small loss of transmission energy using the concept of a cyclic prefix. With the development of modern signal processing technology, OFDM has become practical to implement and has been proposed as an efficient modulation scheme for applications ranging from modems, digital audio broadcast, to next generation high speed wireless data communications. The high speed wireless LAN standard IEEE 802.11a is based on OFDM. Also OFDM is been used for WIMAX and a candidate for 4G technology. This paper is an attempt to understand multiple effects of varying length of cyclic prefix for Additive White Gaussian Noise (AWGN) channel and with Rayleigh fading channel.

In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over Digital Audio Broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a Personal Computer via an USB port. We have implemented the system on an FPGA with an embedded RISC processor. We also describe the tools whose development was needed to ease the IP extractor development and to test the functionality of the system. Finally the results of our tests with two applications of IP data transmission over DAB networks -data carousels and video streaming- are presented.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

OFDM (orthogonal frequency division multiplexing) is usefully applied for DAB (digital audio broadcasting) and DVB (digital video broadcasting) systems due to its high spectral efficiency and robustness to ISI (intersymbol interference) and multipath fading. However, the OFDM signal has a large PAPR (peak-to-average power ratio), which results in significant nonlinear distortion when it passes through an HPA (high power amplifier) such as a TWTA (traveling wave tube amplifier) and a SSPA (solid state power amplifier). We propose a new PAPR reduction method using soft clipping and filtering. Unlike conventional hard clipping, soft clipping has non-zero slope in the clip region. Next, filtering, which uses additional FFT and IFFT processes, is applied in order to reject the out-of-band clip noise. Although the filtering removes the out-of-band noise, it oppositely increases PAPR by a small amount. Since an HPA increases the power consumption according to the linearity range, soft clipping for an SSPA lowers power consumption and is more efficient than the conventional hard clipping method. By the results of the proposed method, the wanted PAPR can be obtained and there is no out-of-band radiation caused by the clipping process.

Digital Audio Broadcasting (DAB)-based demand response for buildings, electric vehicles and prosumers (DAB-DSM)

Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS. Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog

Cognitive radio (CR) is one of the compelling ideas to solve the spectrum scarcity problem for rapid developments in wireless communication systems. In CR systems, signal detection for orthogonal frequency division multiplexing (OFDM) systems in severe noise environments is a key challenge. The area of practical primary user detection has not been explored in depth. The proposed method is an effective method for sensing OFDM applications, which are the practical primary users, for low signal-to-noise (SNR) cases. In the proposed method, the parallel combination of the comb filter and the time-domain autocorrelation function is exploited. The detection performance is measured for various OFDM system applications, including the IEEE 802.11a wireless LAN (WLAN) radio interface, long-term evaluation (LTE), and digital audio broadcasting (DAB) for various CP ratios under 16-quadrature amplitude modulation (16-QAM) and 64-quadrature amplitude modulation (64-QAM) over multipath Rayleigh fading channels with additive white Gaussian noise (AWGN). Furthermore, the OFDM sensing is possible in the presence of noise uncertainty and the sensing performance is compared under consideration with and without noise uncertainty cases. The simulation results demonstrated that our proposed method undoubtedly improves the sensing performances (up to 11 dB SNR gain) of practical primary users more than the conventional spectrum detection methods for low SNR cases.

Orthogonal Frequency Division Multiplexing (OFDM) is a type of Multicarrier Modulation (MCM) technique in which entire bandwidth is divided into large number of small sub-carriers and each subcarrier is transmitted parallel to achieve higher data rates. It has various applications like Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB) and wireless LAN.OFDM technique is widely used in wireless communication system because of its very high data rate. The performance of FFT based OFDM system using Linear and cyclic channel coding and Constant Modulus Algorithm (CMA) equalizer is simulated using simulink model. The BER saving using the optimized proposed model with both linear and cyclic channel coding along with CMA equalizer is evaluated. The proposed work using cyclic channel coding with QPSK/QAM modulation and CMA as channel equalization under AWGN channel results in 52.6% and 96.3% BER reduction as compared to conventional OFDM model without channel coding, channel equalization and channel fading. So, CMA equalizer is used to enhance the performance of OFDM system.

Sending broadcast messages is an efficient means of communicating in emergency situations, especially during serious disasters. This paper focuses on the digital audio broadcast (DAB) system. First, several new techniques are reported to enhance the emergency warning message (EWM) receiving and display functionalities for both personal and public DAB terminals. Then, a novel bidirectional communication method between two DAB transmitters is proposed, to enable the communication to and from the disaster area and the outside. Experiments show that the EWM can be correctly sent to the intended DAB terminals within 0.2–3 s, and the existing public light emitting diode screens can be expanded as DAB EWM terminals without affecting their normal functions. The bidirectional multimedia communication between two DAB transmitters is also successfully demonstrated. The proposed techniques expand upon the DAB’s existing functionality, and can benefit more people during emergencies.