An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm

LDPC codes are finding increasing use in digital communication. The fast-paced evolution of new communication standards and ad-hoc applications requires rapid design iteration. Hand-coded RTL architectures generally provides high performance levels but slower the path to IP creation. In this paper we present a hardware LDPC decoder architecture generated with Vivado HLS from a generic SystemC behavioral model. We evaluate the performance of our approach and assess efficiency versus competing approaches. Throughput speedups between 1.1× and 16.7× are shown with an area improvements of 1.6× to 23.8×. A single LDPC decoder reaches up to 150 Mbps on a Xilinx Virtex-7 device for ten layered decoding iterations.

FGS (fine granularity scalability) is the latest video-coding tool provided in the amendment 4 of MPEG-4 standard. We address a corresponding pair of efficient streaming schedule and pipeline decoding architecture to speed up the decoding process. The design may be applied to the applications of streaming stored FGS video and will benefit other FGS related applications.

Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.

Increased process variation and reduced operating voltage present two of the main challenges in using sense amplifiers for small geometry bulk CMOS process technology. This fact coupled with the need to increase on-chip memory to reduce traffic on the bus and increase performance creates the need for a robust and reliable sense amplifier - a differentiating factor in memory area, power, and speed. We present a detailed study of the Voltage Latched Sense Amplifier (VLSA) and the Current Latched Sense Amplifier (CLSA) design in 28nm industry standard process technology [1][2]. We present results on how the two sense amplifier behave for the two design topology for low power (LP) process technology optimized for mobile low leakage application and the second one is high performance High Performance (HP) applications. Detailed Spice simulation with statistical models and Monte Carlo simulations is utilized to compare the two designs for active power, leakage power, speed, and area. Our study shows that VLSA performs better than CLSA - being 67% faster, 35% smaller area, and similar active power for the LP. The VLSA also performed better than the CLSA is the HP technology as well. The sensitivity to temperature for the LP technology node was more at high voltage but for the HP process the lower voltage perform worse.

This paper propose a new flexible low-density parity-check (LDPC) decoding architecture that can be dynamically reconfigured according to a parity-check matrix which changes as code rate or block length varies. Since the LDPC codes are adopted in standards such as DVB-S2, IEEE 802.1 In and IEEE 802.16e and each standard allows various code rates and block lengths, an LDPC decoder architecture that could support multiple code rates and code block lengths is needed. The proposed architecture employs Benes network to implement configurable interconnection network. In the proposed architecture the number of levels and the delay of the interconnection network is reduced by using broadcasting technique which transmits reduced messages to save the complexity of the interconnection network. The number of processing units in the proposed partially parallel architecture is determined by investigating the relation between hardware complexity and throughput. By applying pipelining to the processing units, decoding throughput is increased. To verify the proposed architecture, a flexible LDPC decoder is implemented using a 0.18 mum CMOS process. The decoder occupies an area of 16.261 mm and runs correctly at the frequency of 212 MHz resulting in 1 Gbps decoding throughput.

Problem statement. Deep neural networks are successfully used in channel coding to improve the quality of decoding. However, modern neural channel decoders cannot achieve high decoding performance and low complexity at the same time. To overcome this problem, it is necessary to develop a decoder with a double residual neuron. By integrating residual input and residual learning into the neural channel decoder architecture, it will significantly improve decoding performance while maintaining low complexity. Goal. Development of a decoder architecture with a dual residual neural network, which provides high decoding performance in channel coding with low model complexity and computational costs. Results. The simulation results show that the proposed decoder with a double residual neural network provides a significant increase in decoding performance. Compared to a neural decoder based on a trust propagation algorithm, a decoder with a dual residual neural network provides an additional 0.5-1.8 dB encoding gain compared to different channel codes. Compared to the hypergraph neural decoder, which has the best error correction capability among all existing neural channel decoders, the dual residual neural network decoder also provides similar or even better decoding performance for different channel codes. Practical significance. The results obtained can be used to improve decoding efficiency and improve performance in channel coding. The work was carried out with the financial support of the Ministry of Science and Higher Education of the Russian Federation within the framework of the state assignment "youth laboratory" No. FZGM-2024-0003.

Parallel turbo decoding techniques to achieve high throughput have been extensively investigated in the literature. These techniques are commonly combined. In this case, the impact on the hardware complexity and on the throughput is usually only accurately determined at the end of the design process. Thus, the time to market is penalized and the probability of designing a sub optimal system increases. In this paper we address this problem by introducing a dedicated approach to efficiently explore the design space of parallel turbo decoder architectures. Using this approach, a tradeoff between the hardware complexity and the throughput can be established in the early stages of the architecture design process. Our approach considers especially memory conflict issues, as well as Soft-Input Soft-Output decoder architectures.

This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. In order to provide sufficient memory bandwidth without the need for using registers, a FIFO-based check-mode memory, which dominates the decoder area, is used. Since two compensation factors, rather than a single factor, are dynamically used in the offset Min-Sum algorithm, the number of quantization bits, and, hence, the memory size, can be reduced without degradation in error performance. In order to further reduce the memory size, artificial minimum values, which do not need to be stored in memory, are used. We also propose an algorithm that can be used to partition variable nodes such that the hardware cost can be minimized. Using the proposed techniques, a multi-standard decoder that supports the LDPC codes specified in the ITU G.hn, IEEE 802.11n, and IEEE 802.16e standards was designed and implemented using a 90-nm CMOS process. This decoder supports 133 codes, occupies an area of 5.529 mm2 , and achieves an information throughput of 1.956 Gbps.

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.

The development of high performance and high density packaging electronic devices has led to the concentration of heat generation in smaller areas, resulting in the formation of "hotspots", i.e., regions of high heat flux. Localized high temperatures can adversely affect the performance of electronic components or cause high thermal stress. Therefore, there is an urgent need to develop thin, high performance cooling devices that can achieve effective heat dissipation in confined spaces. Micro/nanofabrication technologies offer solutions to address these challenges. Heat pipes, as efficient passive cooling devices, are widely used for heat dissipation in various electronic devices. High capillary pumping performance and heat transfer area capillary wicks can be obtained through micro/nanoprocessing technology. This paper presents a comprehensive review on the types and applications of heat pipes and discusses the principles of enhancing heat transfer in heat pipes through micro/nanostructures. Furthermore, summarizes various fabrication methods for micro/nanostructured heat pipes, including chemical and oxidation treatment, laser processing, lithography technology and etching processes, electrical discharge machining, electrochemical deposition and so on. Finally, the characteristics of various fabrication methods together with the issues and challenges faced in the development of heat pipes are presented.

Low complexity Reed–Solomon-based low-density parity-check design for software defined optical transmission system based on adaptive puncturing decoding algorithm

In this letter, we present a design method to find good protograph-based low-density parity-check codes with the numbers of nonzero elements in the parity-check matrix and decoding iterations both strictly limited. We utilize the protograph-based extrinsic information transfer (PEXIT) analysis to evaluate the error performance and employ the differential evolution algorithm to devise a well-performed coding scheme. In particular, the number of iterations in the PEXIT analysis is set to a small value due to the limited iterations in the decoding process. Both numerical analyses and simulations verify that the resulting codes exhibit better performance than conventional code designs under the limitation of decoding complexity.

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

Very low bit-rate F0 coding for phonetic vocoders using MSD-HMM with quantized F0 symbols

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.