Low complexity Reed–Solomon-based low-density parity-check design for software defined optical transmission system based on adaptive puncturing decoding algorithm

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

Low-Density Parity-Check (LDPC) Code has become one of the best coding technologies at present because of its low complexity iterative decoding algorithm and its performance with further close to the Shannon limit. Non-binary LDPC codes designed in high order Galois fields have shown better potential than binary LDPC codes with the same code length and code rate, therefore it was applied for the navigation message encoding in BeiDou satellite navigation system (BDS). The navigation message contains time information, ephemeris parameters, clock correction terms and so forth, which is necessary for navigation solution. As the synchronization head was not encoded, it is hard to deal with data synchronization and navigation data decoding when the navigation receiver works at a low Signal-to-Noise Ratio (SNR). Aiming at this problem, we present a synchronization scheme for BDS B2a signal by utilizing the information from the process of decoding. The synchronizer is based on syndrome checks using the decoding result of the Extended Min-Sum (EMS) algorithm. Ratios of satisfaction of all check restrictions are computed firstly, and then the boundary value is obtained through MonteCarlo method. Simulation results show that the proposed algorithm performs well at relatively low SNR compared with traditional method.

The queued-code based on low-density parity-check (LDPC) codes, which exploit both the near Shannon-limit performance LDPC codes and the instantaneous channel state information (CSI), can provide excellent performance in the block fading channels. The existing work utilized the conventional random puncturing and repetition operation, which may lead to considerable performance loss due to the changed intrinsic connections of parity-check matrix (PCM) for the receiver. In this paper, we present a reversed sequential puncturing (RSP) scheme and a construction method with modified dual-diagonal structure for the LDPC coded queued-code. The consecutive puncturing pattern in reversed direction can ensure the uniform row-weight distribution of the punctured PCM. The modified dual-diagonal form and the RSP scheme can ensure no more than one punctured symbol involved in each check-sum equation. The simulation results demonstrate that our proposed scheme can achieve noticeable performance gains.

Multi-rate low-density parity-check (LDPC) codes are widely used in satellite communication (SatCom) systems due to their outstanding performance and adaptable code rates. However, their hardware decoder implementations typically require high hardware resources and many decoding iterations, which pose challenges for high-throughput applications in resource-constrained, high-data-rate SatCom scenarios. To this end, the design of throughput-optimized multi-rate LDPC codes is investigated, aiming to tackle the decoder implementation problem from the perspective of practical code design. Specifically, a multi-rate weighted normalized throughput metric is introduced, which considers two key factors, i.e., the number of non-zero elements in the parity-check matrix and the required decoding iterations. Then, the throughput-optimized multi-rate code design problem is formulated to maximize the proposed metric under given decoding threshold constraints, which is later solved using a protomatrix search method based on the differential evolution (DE) algorithm. Finally, three multi-rate LDPC codes are optimized for scenes with different code rate usage frequencies. Their performance is extensively evaluated both theoretically and numerically. Results demonstrate that the proposed codes outperform other similar LDPC codes in the literature, showing a throughput increase of 20% to 30% under the same hardware resource consumption.

The increasing demand for high-density and high-speed digital optical recording systems has made the development of advanced coding and signal processing techniques for fast and reliable data recovery increasingly important. In recent years, the parity-check (PC)-code-based reception technique has been widely studied for magnetic recording systems, and it is projected to be highly promising for high-density optical recording. The PC code is an inner error correction code (ECC), which can detect dominant short error events of the system, using only a few parity bits. This reduces the loss in error correction capability of the outer ECC due to random short errors and results in a simple and efficient solution to improve the overall performance. This thesis is dedicated to the design and analysis of PCcode- based recording systems to achieve higher recording capacity with low implementation complexity, for high-density blue laser disc systems. In particular, most of the key components of the PC-code-based optical recording system have been designed and optimized for different recording densities, and different proportions of white noise and media noise. During the development of advanced coding and detection techniques, it becomes necessary to investigate the system’s performance with different coding schemes and recording densities. In Chapter 2 of the thesis, we propose a generalized Braat-Hopkins model for optical recording channels, which provides a fair basis for the performance comparison of detection schemes over different coding schemes and recording densities, for channels with additive, white Gaussian noise (AWGN) and media noise. Various basic issues associated with the PC-code-based systems are investigated in Chapter 3. These include bounds for bit error rates and error event probabilities, the dominant error events at channel detector output, different PC codes, simple and efficient post-processors, the impact of error events that are split across data block boundaries and the corresponding remedy, as well as the effects of code rates and recording densities. Simulation results show that a 4-bit PC code achieves the best performance. The corresponding bit error rates (BERs) are very close to the performance bounds, at both nominal and high densities. Constrained codes, which serve as a key component in the read-write channel of data storage systems, are desired to have a high code rate with low-complexity encoder/decoder. In Chapter 4, we investigate the design of certain capacity-approaching constrained codes for optical recording systems. In particular, we derive analytically the relationship between the number of encoder states and the maximum size of these codes. We identify the minimum number of encoder states that maximizes the code rate, for any desired codeword length. The design of constrained PC codes is key to the development of PCcode- based systems, and the systematic design of efficient constrained PC codes remains a challenging problem. In Chapter 5, we propose a general and systematic code design technique for constructing capacity-approaching constrained PC codes, which can detect any type of error events of the system, with the minimum code rate loss. Compared to the rate 2/3 code without parity, the newly designed constrained 4-bit PC code achieves a performance gain of 2 dB at nominal density, and 1.5 dB at high density, at BER = 10-5. As the dominant noise for high-density optical recording systems, media noise severely degrades the performance of channel detectors and postprocessors that are designed for AWGN. In Chapter 6, we propose two novel modifications to the bit detector to combat media noise. We further develop a data-dependent post-processing scheme for error correction. Compared to the system designed without considering media noise and without PC codes, the overall performance gain of the developed scheme can be more than 11 dB at high media noise levels. In data storage systems, the ECC failure rate (EFR) serves as the ultimate measure of the data recovery performance. In Chapter 7, we develop semi-analytical approaches for estimating the EFR, and analyze EFRs for the developed PC-code-based systems, for the cases without and with interleaving. Our analysis shows that with the optimum interleaving degrees, compared to the rate 9/13 code without parity, the 2-bit PC code achieves a gain of around 0.5 dB, and the 4-bit PC code gains 0.6 dB, at high record ing density and EFR = 10-16. The thesis concludes in Chapter 8 with some suggestions for further work.

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of E_b/N_0 until the BER of 1e−6.

Structured quasi-cyclic LDPC codes with girth 18 and column-weight [formula omitted

Several combinatorial properties of low-density parity-check (LDPC) codes, such as minimum distance, diameter, stopping number, girth and cycle-length distribution of the corresponding Tanner graph, are known to influence their performance under iterative decoding. Recently, a new class of combinatorial configurations, termed trapping sets, was shown to be of significant importance in determining the properties of LDPC codes in the error-floor region. Very little is known both about the existence/parameters of trapping sets in structured LDPC codes and about possible techniques for reducing their negative influence on the code's performance. In this paper, we address both these problems from an algorithmic and combinatorial perspective. We first provide a numerical study of the trapping phenomena for the Margulis code, which exhibits a fairly high error-floor. Based on this analysis, conducted for two different implementations of iterative belief propagation, we propose a novel decoding process, termed averaged decoding. Averaged decoding provides for a significant reduction in the number of incorrectly decoded frames in the error-floor region of the Margulis code. Furthermore, based on the results of the algorithmic approach, we suggest a novel combinatorial characterizations of trapping sets in the class of LDPC codes based on finite geometries. Projective geometry LDPC codes are suspected to have extremely low error-floors, which is a property that we may attribute to the non-existence of certain small trapping sets in the code graph.

This paper gives necessary and sufficient conditions for the Tanner graph of a quasi-cyclic (QC) low-density parity-check (LDPC) code based on the all-one protograph to have girth 6, 8, 10, and 12, respectively, in the case of parity-check matrices with column weight 4. These results are a natural extension of the girth results of the already-studied cases of column weight 2 and 3, and it is based on the connection between the girth of a Tanner graph given by a parity-check matrix and the properties of powers of the product between the matrix and its transpose. The girth conditions can be easily incorporated into fast algorithms that construct codes of desired girth between 6 and 12; our own algorithms are presented for each girth, together with constructions obtained from them and corresponding computer simulations. More importantly, this paper emphasizes how the girth conditions of the Tanner graph corresponding to a parity-check matrix composed of circulants relate to the matrix obtained by adding (over the integers) the circulant columns of the parity-check matrix. In particular, we show that imposing girth conditions on a parity-check matrix is equivalent to imposing conditions on a square circulant submatrix obtained from it.

In this chapter we cover some of the more common applications of LDPC codes. The breadth and depth of work reported in the literature on the application of LDPC codes to data transmission and storage would fill many volumes. Thus, this chapter has the modest goal of introducing selected applications. These applications include coded modulation, turbo equalization and code design for intersymbol-interference channels, estimation of the level LDPC error floors, and decoder design for low error floors. We also provide in this chapter a brief introduction to LDPC convolutional codes. Because of their importance, we also include a section on so-called digital fountain codes, which have application to file transfer over networks and closely resemble LDPC codes.

This paper presents an enhanced partially-parallel low-density parity-check (LDPC) decoder based on Consultative Committee for Space Data Systems (CCSDS) standard for high speed near Earth applications. Architectural level optimization is exploited to reduce hardware complexity and increase decoding throughput. To enchance the parallelism of the partially-parallel decoder, high circulant weight submatrix of the parity check matrix (PCM) are partitioned into several identity matrices with corresponding cyclic-shifted value and processed separately. Furthermore, messages corresponding to adjacent rows of the cyclic-shifted identity matrix are stored in one memory entry, and low-complexity data aligners are designed between memories and processing units to avoid memory access conflicts. Hardware implementation of a (8176,7154) LDPC code on Xilinx Virtex-5 XC5VLX330 FPGA shows that the proposed decoder can achieve a decoding throughput of 1.02 Gb/s at 10 iterations.

In this paper, a random Low-Density Parity-Check (LDPC) code is proposed for Noncontiguous Orthogonal Frequency Division Multiplexing (NC-OFDM) Cognitive Radio (CR) systems. Unlike other encoding schemes which achieve a system code rate of only 1/4 when half of the subcarriers are active, the proposed scheme achieves a system code rate of 1/2. The LDPC code is used to enhance the data transmission rate. A new channel model comprised of a binary erasure channel concatenated with an uncorrelated fading channel and an AWGN channel is adopted for NC-OFDM CR systems. Moreover, the adopted channel model is employed with density evolution algorithm to obtain good degree distribution pairs for the LDPC code. Thereafter, a modified shortest-path algorithm is used to construct the parity-check matrix for the LDPC code. Simulation results show that the proposed LDPC code performs well in terms of both error rate and data transmission rate.

Nonbinary LDPC coding is a class of excellent error correcting codes in wireless communication systems. The hardware realization of this decoder architecture put forth a challenge at making a better tradeoff between the computation complexities and decoding performance. This letter proposes modifications in the structure of H-matrix which characterizes the Low Density Parity Check (LDPC) codes. The modification is aimed towards the reduction of computation complexity by retaining the properties of H-matrix. Two masking matrices are proposed with reduced number of non- zero elements, forming the diagonals of the parity check matrix. Simulation results indicate improved decoding performance and reduced computational complexity with the proposed H-matrix structures.

This chapter discusses fundamentals of information theory and channel coding (error correction coding ECC, Forward error correction FEC). First, key results of Shannon, including channel capacity and the relationship between transmit power and bandwidth, are discussed. Block codes multiply a block of data with an encoding matrix. For systematic codes, the resulting codeword consists of systematic bits and parity check bits. Decoding is achieved by multiplication with a parity check matrix and determination of the syndrome vector. Correction of errors within the correction sphere can be done, e.g., through lookup tables. Convolutional codes send the source data stream through shift registers and adders, a process described by a trellis diagram. Maximum-likelihood sequence estimation (Viterbi algorithm) determines the (transmit) bit sequence with best distance metric (Hamming or Euclidean) from the received signal. Methods for combining coding and higher-order modulation include trellis coded modulation (using set partitioning for code design) and bit-interleaved coded modulation (BICM). Turbo codes are close to capacity-achieving. They are based on transmitting differently interleaved convolutional codes; receivers use soft decoding of the constituent codes and iterative exchange of soft information (log-likelihood ratios). Low-density parity check codes (LDPCC) are decoded by belief propagation (message passing), where variable nodes and constraint nodes exchange beliefs about the codeword. In fading channels, (block or convolutional) interleaving is essential to provide diversity. From an information-theoretic point of view, in fading channels we can distinguish between the ergodic capacity and the outage capacity. If the channel state information is known at the transmitter, waterfilling is the optimum power allocation strategy. Automatic Repeat Request ARQ) and Hybrid ARQ (including chase combining or incremental redundancy) are described in the appendix.