An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies

Existing statistical static timing analysis (SSTA) techniques suffer from limited modeling capability by using a linear delay model with Gaussian distribution, or have scalability problems due to expensive operations involved to handle non-Gaussian variation sources or non-linear delays. To overcome these limitations, we propose a novel SSTA technique to handle both nonlinear delay dependency and non- Gaussian variation sources simultaneously. We develop efficient algorithms to perform all statistical atomic operations (such as max and add) efficiently via either closed- form formulas or one-dimensional lookup tables. The resulting timing quantity provably preserves the correlation with variation sources to the third-order. We prove that the complexity of our algorithm is linear in both variation sources and circuit sizes, hence our algorithm scales well for large designs. Compared to Monte Carlo simulation for non-Gaussian variation sources and nonlinear delay models, our approach predicts all timing characteristics of circuit delay with less than 2% error.

1) For correct operation of a slideback voltmeter which measures pulsed voltages, it is not necessary to aim at a minimum threshold operating voltagev of the indicator, but at a value ofv which meets the requirements given in (3) or (9). Eqs. (3) and (9) do not provide separate values forv and R, but only determine the relation between them and the diode parameters A andk. The choice ofv and R is more or less arbitrary. One consideration for choosing R should consist in providing sufficient time for capacitance CL to discharge between the pulses. 2. The measurement error due to the error or the instability of the indicator's threshold of operation or the diode load resistor can be computed from (6) and (7). 3. By choosing the load capacitance CL by means of (17) it is possible to reduce the voltmeter error due to transient processes. Since the value of CL in (17) depends on the measured voltage, it may be advisable to couple the adjustment of the compensating voltage E with that of capacitance CL.

The data path and memory elements are integral hardware components to evaluate the performance of a complex ASIC low power architecture. In this study, a FinFET model was evaluated via 7 nm FinFET process using ASAP PDK and applied to 6T SRAM cells and 32-bit ALU architecture. Devices of 0.207 V threshold were biased at 0.7V supply voltage. The clock router was properly modeled with accurate values of resistances and capacitances for the metal layers. The noise glitch and cross talk within the parallel running interconnects and the driving loads were incorporated in the model. A command set clock uncertainty is also integrated into the model to incorporate the clock jitter and clock skew effects. The architecture was optimized for worst case scenario with typical RC corners. The Non-Linear Delay Model (NLDM) was incorporated for the cell synthesis where a delay that is based on the input transition and output load capacitance was incorporated for better quality of results (QoR). The low power architecture was evaluated for worst case scenario considering typical-typical (TT) corners. A maximum effective device current of 18.26µA with subthreshold slope of 60mV/decade were estimated and considered in the system evaluation. The output ports were loaded with a typical 2fF capacitance. At 1 GHz operation, the internal power, switching power, and leakage power are reported to be 0.2705 mW, 0.7599 mW, and 0.00743 mW, respectively.

Body biasing is a well-known circuit technique to compensate for increasing process variations. A static body biasing, in which fixed amount of bias voltage is applied after chips are sorted out according to process corners, is a convenient and viable approach in ASIC designs. The key question in this approach is how we generate new gate delays without re-characterizing all the gates, which is expensive. We notice, for the first time, that the ratio of delay (of original gate and the gate after body biasing) from the time input starts to change to the time output crosses V dd =2 can be regarded invariant, i.e. it is a function of input transition time and load capacitance, but not a function of gate type. Therefore, once the ratio is characterized using a sample gate such as an inverter, it can be used to derive delay of all the other gates. We also propose some refinement techniques to improve accuracy. Experiments with industrial 32-nm library indicate that the average error over re-characterization is about 4% with maximum error being 11%, when maximum body bias voltage is assumed. The errors decrease as smaller bias voltage is applied.

Power consumption has become hurdle for recent IC design as technology scale down below 45nm. Aggressive nanoscaling of MOS transistor in process technology has advanced in chip density, but to achieve high performance and lower power consumption by continues scaling results in shorter channel effect and Lowering of Drain Induced Barrier Lowering (DIBL). To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper we have utilize the property of FinFET technology in SRAM circuit design to lower power consumption. Proposed circuit shows maximum saving of dynamic power up to 76.57% in 4T, maximum leakage power saving up to 53.21% in 6T at 25°C and 45.13% at 110°C. All simulation is performed using HSPICE simulator by using Berkley Productive Technology model (BPTM) at 32nm.

As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCmin</sub> ) of the SoC because of the large threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) mismatch between paired transistors caused by small feature size. As process technology scales down to sub-32nm technology, the 6T SRAM bitcell that is currently used may not achieve proper stability, write-ability, and read-ability at the required operating voltage. In this paper, several approaches are investigated to resolve the issue, such as upsized 6T SRAM bitcell, 8T SRAM bitcell, read- and write-preferred bitcells, and read- and write-assist circuits. HSPICE simulations are performed using PTM 32nm model parameters.

With the technology scaling and shrinking feature sizes, coupling noise has become one of the most critical concerns in today's interconnect-centric design, especially for long global buses. A very common consequence of coupling is that the output signal waveform becomes non-monotonic. Traditionally, only through circuit simulation can the output waveform can be precisely acquired. However, this method suffers from low efficiency especially for today's super scale circuits. This paper proposes a fast algorithm to accurately estimate the output waveform for buses at the presence of coupling noise. Experimental results show that only a little more than 2% mean error is induced while, on average, the running time of the proposed algorithm is 23 times faster than HSPICE simulation.

We present an evaluation of the silicon solar cell as well as the photovoltaic (PV) module size and its effect on thermomechanical stress. The evaluation is based on finite-element method (FEM) simulations. Within these simulations, we perform parameter variations of the number of solar cells within a PV module from 60–140 cells, of the cell size from 156.0–161.75 mm, and the cell format from full cells down to quarter cells. The FEM simulations cover the lamination process, mechanical load, and thermal cycling for glass–foil as well as glass–glass modules. The presented results reveal correlations between the solar cell and module size with the stress in the solar cells. We also find that the interaction of the laminate with the module frame plays a significant role in thermal cycling. Of the varitations under investigation, the increase in cell size has the largest effect on the stress. However, at a mechanical load of 2400 Pa, glass–foil modules with less than 96 solar cells have a negligible failure probability. The advantage of placing the solar cells in the neutral axis of the laminate is proven by the negligible tensile stress values for all variations of the glass–glass modules.

Complex periodic patterns can self-organize through dynamic interactions between diffusible activators and inhibitors. In the biological context, self-organized patterning is challenged by spatial heterogeneities ('noise') inherent to biological systems. How spatial variability impacts the periodic patterning mechanism and how it can be buffered to ensure precise patterning is not well understood. We examine the effect of spatial heterogeneity on the periodic patterning of the fruit fly eye, an organ composed of ∼800 miniature eye units (ommatidia) whose periodic arrangement along a hexagonal lattice self-organizes during early stages of fly development. The patterning follows a two-step process, with an initial formation of evenly spaced clusters of ∼10 cells followed by a subsequent refinement of each cluster into a single selected cell. Using a probabilistic approach, we calculate the rate of patterning errors resulting from spatial heterogeneities in cell size, position and biosynthetic capacity. Notably, error rates were largely independent of the desired cluster size but followed the distributions of signaling speeds. Pre-formation of large clusters therefore greatly increases the reproducibility of the overall periodic arrangement, suggesting that the two-stage patterning process functions to guard the pattern against errors caused by spatial heterogeneities. Our results emphasize the constraints imposed on self-organized patterning mechanisms by the need to buffer stochastic effects. Author summary Complex periodic patterns are common in nature and are observed in physical, chemical and biological systems. Understanding how these patterns are generated in a precise manner is a key challenge. Biological patterns are especially intriguing, as they are generated in a noisy environment; cell position and cell size, for example, are subject to stochastic variations, as are the strengths of the chemical signals mediating cell-to-cell communication. The need to generate a precise and robust pattern in this 'noisy' environment restricts the space of patterning mechanisms that can function in the biological setting. Mathematical modeling is useful in comparing the sensitivity of different mechanisms to such variations, thereby highlighting key aspects of their design.We use mathematical modeling to study the periodic patterning of the fruit fly eye. In this system, a highly ordered lattice of differentiated cells is generated in a two-dimensional cell epithelium. The pattern is first observed by the appearance of evenly spaced clusters of ∼10 cells that express specific genes. Each cluster is subsequently refined into a single cell, which initiates the formation and differentiation of a miniature eye unit, the ommatidium. We formulate a mathematical model based on the known molecular properties of the patterning mechanism, and use a probabilistic approach to calculate the errors in cluster formation and refinement resulting from stochastic cell-to-cell variations ('noise') in different quantitative parameters. This enables us to define the parameters most influencing noise sensitivity. Notably, we find that this error is roughly independent of the desired cluster size, suggesting that large clusters are beneficial for ensuring the overall reproducibility of the periodic cluster arrangement. For the stage of cluster refinement, we find that rapid communication between cells is critical for reducing error. Our work provides new insights into the constraints imposed on mechanisms generating periodic patterning in a realistic, noisy environment, and in particular, discusses the different considerations in achieving optimal design of the patterning network.

Development of high thermal insulation and compressive strength BPP foams using mold-opening foam injection molding with in-situ fibrillated PTFE fibers

In deep sub-micron technology, accurate modeling of output waveforms of library cells under different input slew and load capacitance values is crucial for precise timing and noise analysis of VLSI circuits. Construction of a compact and efficient model of such waveforms becomes even more challenging when manufacturing process and environmental variations are considered. This paper introduces a rigorous and robust foundation to mathematically model output waveforms under sources of variability and to compress the library data. The proposed approach is suitable for today's current source model (CSM) based ASIC libraries. It employs an orthonormal transformation to represent the output waveforms as a linear combination of some appropriately-derived basis waveforms. More significantly Robust Principle Component Analysis (RPCA) is used to stratify the library waveforms into a small number of groups for which different sets of principle components are calculated. This stratification results in a very high compression ratio for the variational CSM library while meeting a maximum error tolerance. Interpolation and further compression is obtained by representing the coefficients as signomial functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. We propose a procedure to calculate the coefficients and power of the signomial functions. Experimental results demonstrate the effectiveness of the proposed variational CSM modeling framework and the stratification-based compression approach.

A gain-boost class-C inverter that simultaneously targets high DC gain and wide output swing is proposed in this study. Unlike those of the traditional gain-boost class-C inverter, the input transistors of the proposed gain-boost circuit for the PMOS cascode circuit are n type, whereas those for the NMOS cascode circuit are p type. Consequently, the output swing of the proposed gain-boost class-C inverter is unrestricted by the gain-boost circuit, and thus, a wide output swing can be achieved. A self-cascode structure is also adopted for the gain-boost circuit, thereby allowing it to obtain high DC gain. When compared with the traditional gain-boost class-C inverter with the same input transistor size, power consumption, and load capacitance, simulation results show that the proposed gain-boost class-C inverter improves DC gain by over 35% and boost output swing by over 20%.

As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at various levels of the computation stack. The error rates would be especially high for post-CMOS and nanoelectronic systems as well as for probabilistic [3] and stochastic architectures [4]. N-modular redundancy (NMR) at the core-level has been proposed as a way to attain system reliability goals for multicore architectures. While core-level DMR and TMR have been shown to be effective when errors are rare, a large amount of core-level redundancy will be required for attaining system reliability goals in face of high error rates. This makes voting latency and bandwidth significant performance bottlenecks for such systems. In this paper, we present a scalable NMR framework for error prone chip multiprocessors(CMPs). The framework supports in-network fault tolerance where voting logic is integrated into routers to allow for truly distributed voting. The in-network fault tolerance router utilizes the expected redundancy in vote messages, to reduce some of the blocking overhead incurred at the leader, and also provide a mechanism to trade-off network bandwidth with latency. Our framework also supports proactive checkpoint deallocation which allows cores participating in voting to continue on with execution instead of waiting on notification from the voting logic. Finally, the framework supports dynamic constitution that allows an arbitrary core on this chip to be a part of an NMR group. This allows bypassing faulty cores as well as scheduling for performance. Our experiments show significant performance/bandwidth benefits from these optimizations.

Tungsten trioxide adopts a variety of structures which can be intercalated with charged species to alter the electronic properties, thus forming ``tungsten bronzes.'' Similar effects are observed upon removing oxygen from $\mathrm{W}{\mathrm{O}}_{3}$. We present a computational study of cubic and hexagonal alkali bronzes and examine the effects on cell size and band structure as the size of the intercalated ion is increased. With the exception of hydrogen (which is predicted to be unstable as an intercalate), the behavior of the bronzes are relatively consistent. $\mathrm{Na}\mathrm{W}{\mathrm{O}}_{3}$ is the most stable of the cubic systems, although in the hexagonal system the larger ions are more stable. The band structures are identical, with the intercalated atom donating its single electron to the tungsten $5d$ valence band. A study of fractional doping in the ${\mathrm{Na}}_{x}\mathrm{W}{\mathrm{O}}_{3}$ system $(0\ensuremath{\leqslant}x\ensuremath{\leqslant}1)$ showed a linear variation in cell parameter and a systematic shift in the Fermi level into the conduction band. In the oxygen-deficient $\mathrm{W}{\mathrm{O}}_{3\ensuremath{-}x}$ system the Fermi level undergoes a sudden jump into the conduction band at around $x=0.2$. Lastly, three compounds of a layered $\mathrm{W}{\mathrm{O}}_{4}∙\ensuremath{\alpha},\ensuremath{\omega}$-diaminoalkane hybrid series were studied and found to be insulating, with features in the band structure similar to those of the parent $\mathrm{W}{\mathrm{O}}_{3}$ compound that relate well to experimental UV-visible spectroscopy results.

A review of proton migration and interaction energies in doped barium zirconate