Gate delay modeling for static timing analysis of body-biased circuits

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power saving by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

The threshold voltage of the MOSFET is the minimum voltage required to turn on the MOSFET device. The MOSFET threshold voltage can be increased or decreased by applying the proper body potential. The body voltage is known as body bias voltage. The possible ways of body biasing are explored in this chapter. The impact of the various body bias voltages is studied on the MOSFET input characteristics and output characteristics of the MOSFET device. The MOSFET under study are 45nm channel length. This is also known as 45nm Technology. The body bias is studied in PMOS and NMOS devices. The active body bias approach is explored. Reverse body bias is explored to increase the threshold voltage of the PMOS and NMOS devices.

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For digital signal processing (DSP) hardware, variations in circuit parameters can significantly affect the quality of service (QoS). Existing post-silicon calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, frequency, or body bias and typically incur large delay or power overhead. This paper presents a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least significant bits. Hence, truncation of these bits, by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. The proposed technique is applied to two common DSP blocks, namely discrete cosine transform (DCT) and finite impulse response (FIR) filter. Simulation results show significant reduction in critical path delay along with a graceful degradation in the QoS. They also show large improvement in manufacturing yield (41.6%) with up to 5X savings in power compared to existing approaches such as voltage scaling and body biasing.

Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, and a control unit dynamically changes frequency, voltage, and body bias for optimum performance and energy efficiency. Fast response to droops and temperature changes is enabled by a multi-PLL clocking unit and on-chip body bias. Adaptive techniques are also used to compensate performance degradation due to device aging, reducing the aging guardband.

In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits is developed. The tuning methodology is driven by a ?tunable? gate design that allows the gate to be switched from a high-speed/high-power mode to a low-speed/low-power mode under digital control. A small number of ?critical? logic gates are replaced with tunable gates for post-silicon power-performance tuning. In addition, supply voltage and body bias can be employed as hardware ?tuning knobs? as well to deal with delay and leakage variations. After silicon is manufactured, the hardware ?knobs? are programmed through the use of an implicit self-test methodology that can be exercised by the proposed self-adaptation architectural framework. It is seen that the delay yield can be improved by an average of 40% with minimal impact on area.

Many visual quality metrics are used to measure the quality of lossy compressed images and videos, and are integrated in the rate-distortion optimization of hybrid video codecs. However, most of the metrics focus on the average objective quality in a picture. In certain applications, like medical image processing, the maximum absolute error should be more weighted. In this paper, the rate-distortion optimization of HEVC is extended by integrating this error metric. Thus, rate, average error, and maximum absolute error are jointly optimized. Furthermore, a weighting factor α is included into the calculation of the optimization for balancing the ratio between average and maximum absolute error. For HEVC intra with $\alpha =0.25$ an average maximum absolute error reduction of −25.63 can be achieved, while the bitrate increases slightly by 0.59%. Furthermore, the visual quality of the medical volumes improves and the data fidelity increases, i.e. less block artifacts appear and less structure disappear.

Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective Current Source Model (ECSM), which stores certain predefined Threshold Crossing Point (TCP) of the output voltage waveform with respect to different input transition time (TR) values and load capacitance (Cl). In this work, we propose an analytical timing model relating 10% - 90% TCPs with Cl and TR values. We also derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum relative error of 2.5%. We verified the proposed model with technology scaling. We use this model and the relationships to reduce the number of simulations in ECSM library characterization.

Self-assembled monolayers (SAMs) of ferrocene-substituted thiofluorene on Au(111) exhibit two distinct conductance states (CSs) in two-terminal junctions featuring a sharp tip of eutectic GaIn as the top electrode. The occurrence of these states and the resulting effective rectification by the SAM depend on the way the bias voltage is swept; when the junction is only negatively biased, the original, high CS is preserved, whereas the junction is switched to a low CS when applying only positive biases. This results in an exceptionally high effective rectification ratio (RR) of ∼2100 already at voltages as low as 0.1 V. In contrast, when sweeping the junction alternatingly to the maximum positive and negative bias voltages (as usually performed in the literature), fully symmetric J-V curves are observed. That is, for the present SAM, rectification disappears, and the effective RR is ≈1. It is noteworthy that whether the junction in these symmetric sweeps is in the high or low CS depends on the polarity of the first sweep. We attribute the occurrence of the two CSs to a (quasi) non-reversible oxidation of the ferrocenes in combination with structural changes in the monolayer geometry. The observed sweeping dependence of the conductivity switching is an additional parameter that needs to be considered when interpreting experimental J-V curves, especially when dealing with redox-active systems.

A design methodology for gate delay and gate interval time for at-grade crossings using four-quadrant gates is developed. The design approach is based on the concept of dilemma zones related to signal change intervals at signalized intersections. The design approach is validated based on data from six sites in Illinois on a proposed high-speed rail corridor. Gate delay and gate interval times are determined that provide an optimal safe decision point to allow a driver to stop before the crossing or to proceed through the crossing without becoming trapped by the exit gates.

This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$k$</tex></formula> /metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy.

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves -64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuous-time common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68°. Sufficient performance is maintained over process, supply voltage and temperature variations.

Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes a new transmission-gate approach to filter out soft errors, and it is more efficient when to the thanks to its to compared state of art solutions, capability adjust gate and body bias voltages.

An FPGA with field-programmable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> components can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) of transistors. Since V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> for transistors for a specific circuit block in an FPGA is chosen from a set of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> values defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> method. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> components was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th </sub> transistor in a BBVS reveals that deep reverse body bias for high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> transistor does not necessarily offer the optimal condition, and optimization is necessary