An efficient read approach for memristive crossbar array

This chapter introduces resistive random-access memory (RRAM), a futuristic memory technology that excels its counterparts in terms of reliability, nano-scale dimensions, energy per bit, and fast read/write times. Also, it is promising for use in neuromorphic computing and digital applications. However, the major challenge encountered during the progress of the technology is the presence of leakage current (sneak path current) while using it in crossbar arrays. Various techniques are employed to mitigate the sneak current problem. However, associating a selector with RRAM is an efficient method. To study the one selector-one RRAM (1S-1R) characteristics, the electrical model of the selector, as well as RRAM, is necessary; therefore, this chapter discusses the electrical modeling of selector device (1S), RRAM devices (1R), integration of selector models with the RRAM model (1S-1R), and formation of 1S-1R crossbar arrays. The selector device used to model this is Pt/Ta2O5/TaOx /TiO2/Pt, and the RRAM model adopted is Pt/Ta2O5/TaOx/Pt. Further, various parameters are analyzed, such as R off /R on ratio, nonlinearity, and off-current are improved in the 1S-1R cell compared to RRAM characteristics. Besides, it is perceived that 98% of the sneak path current is mitigated in the 1S-1R crossbar array compared to the 1R crossbar array.

Resistance random access memory (RRAM) based on resistive switching in metal oxides has attracted considerable attention as a promising candidate for next-generation nonvolatile memory due to its high operating speed, superior scalability, and low power consumption. However, some operating parameters of RRAM cannot meet the practical requirement, which impedes its commercialization. A lot of experimental results show that doping is an effective method of improving the performance of RRAM, while the study on the physical mechanism of doping is rare. It is generally believed that the formation and rupture of conducting filaments, caused by the migration of oxygen vacancies under electric field play a major role in resistive switching of metal oxide materials. In this work, the first principle calculation based on density functional theory is performed to study the effects of transition metal element X (X=Mn, Fe, Co, and Ni) doping on the migration barriers and formation energy of oxygen vacancy in ZnO. The calculation results show that the migration barriers of both the monovalent and divalent oxygen vacancy are reduced significantly by Ni doping. This result indicates that the movement of oxygen vacancies in Ni doped ZnO is easier than in undoped ZnO RRAM device, thus Ni doping is beneficial to the formation and rupture of oxygen vacancy conducting filaments. Furthermore, the calculation results show that the formation energy of the oxygen vacancy in ZnO system can be reduced by X doping, especially by Ni doping. The formation energy of the oxygen vacancy decreases from 0.854 for undoped ZnO to 0.307 eV for Ni doped ZnO. Based on the above calculated results, Ni doped and undoped ZnO RRAM device are prepared by using pulsed laser deposition method under an oxygen pressure of 2 Pa. The Ni doped ZnO RRAM device shows the optimized forming process, low operating voltage (0.24 V and 0.34 V for Set and Reset voltage), and long retention time (>104 s). Set and Reset voltage in Ni doped ZnO device decrease by 80% and 38% respectively compared with those in undoped ZnO device. It is known that the density of oxygen vacancies in the device is dependent on the oxygen pressure during preparation. The Ni doped ZnO RRAM device under a higher oxygen pressure (5 Pa) is also prepared. The Ni doped ZnO RRAM device prepared under 5 Pa oxygen pressure shows a little higher Set and Reset voltage than the device prepared under 2 Pa oxygen pressure, while the operating voltages are still lower than those of undoped ZnO RRAM. Thus, the doping effect in the ZnO system is affected by the density of oxygen vacancies in the device. Our work provides a guidance for optimizing the performance of the metal oxide based RRAM device through element doping.

Resistive RAM (ReRAM)-based in-memory computing (IMC) is a promising alternative to traditional architectures for achieving energy-efficient and high-performance computing. This study explores the implementation of matrix multiplication in ReRAM-based IMC, a fundamental operation in machine learning and AI accelerators. Various ReRAM models are analyzed, including Stanford RRAM, JART VCM v1b and JART VCM v1b var, with the latter demonstrating superior accuracy. The study further investigates different ReRAM array configuration, such as 1T1R, 2T2R, and crossbar arrays, evaluating their effectiveness in enabling parallel computation and efficient data storage. A key challenge addressed is the sneak-path problem in cross-bar architectures, which is mitigated through optimized circuit designs. Simulation results confirm that ReRAM-based matrix multiplication can significantly enhance computational efficiency, reduce power consumption, and improve memory reliability. Additionally, a perceptron-based NAND gate implementation is demonstrated, showcasing the potential of ReRAM for logic-in-memory applications.

Nowadays, advancements in the design of trusted system environments are relying on security provided by hardware‐based primitives, while replacing resource‐hungry software security measures. Emerging nonvolatile memory devices are promising candidates to provide the required hardware security functionalities at very low area‐energy‐runtime budget. Resistive random access memory (RRAM) offers high‐density integration with outstanding performance among the state‐of‐the‐art nonvolatile memory devices. The RRAM device technology is currently getting significant attention from both academia and industry for constructing beyond Von Neumann architectures. This technology's strength is its scalable two‐terminal structure, the availability of wide range of functional materials, and multi‐bit storage capability. The fluctuations in switching resistances, random telegraph noise, and sneak path current are detrimental characteristics of RRAM integrations for storage and in‐memory computing applications, and more research focuses on alleviating these effects. Interestingly, these characteristics make them suitable for designing security hardware. In recent times, there has been significant progress in the design and analysis of RRAM‐based security primitives such as, Physical Unclonable Function, true random number generator, and hash function. This review discusses the detailed developments in RRAM security and presents the demanded security requirement and available opportunities to be explored.

Improved rectification characteristics by engineering energy barrier height in TiOx-based RRAM

Resistive random access memories (RRAM), based on the formation and rupture of conductive nanoscale filaments, have attracted increased attention for application in neuromorphic and in-memory computing. However, this technology is, in part, limited by its variability, which originates from the stochastic formation and extreme heating of its nanoscale filaments. In this study, we used scanning thermal microscopy (SThM) to assess the effect of filament-induced heat spreading on the surface of metal oxide RRAMs with different device designs. We evaluate the variability of TiO2 RRAM devices with area sizes of 2 × 2 and 5 × 5 μm2. Electrical characterization shows that the variability indicated by the standard deviation of the forming voltage is ∼2 times larger for 5 × 5 μm2 devices than for the 2 × 2 μm2 ones. Further knowledge on the reason for this variability is gained through the SThM thermal maps. These maps show that for 2 × 2 μm2 devices the formation of one filament, i.e., hot spot at the device surface, happens reliably at the same location, while the filament location varies for the 5 × 5 μm2 devices. The thermal information, combined with the electrical, interfacial, and geometric characteristics of the device, provides additional insights into the operation and variability of RRAMs. This work suggests thermal engineering and characterization routes to optimize the efficiency and reliability of these devices.

As transistors start to approach fundamental limits and Moore's law slows down, new devices and architectures are needed to enable continued performance gains. New approaches based on RRAM (resistive random access memory) or memristor crossbars can enable the processing of large amounts of data[1, 2]. One of the most promising applications for RRAM crossbars is brain inspired or neuromorphic computing[3, 4].

Resistive random access memory (RRAM) is one of the universal memory candidates for computer systems. Although RRAM promises many attractive advantages (e.g., huge data storage, smaller form-factor, lower power consumption, non-volatility, etc.), there are many open issues that still need to be solved, especially those related to its quality and reliability. For instance, open defects may cause RRAM cell to enter an undefined state (i.e., somewhere between logic 0 and 1), making it hard to detect during manufacturing test. As a consequence, this may lead to test escapes (quality issue) and field failures (reliability issue). This paper shows - based on defect and circuit simulation - how testing RRAM is different from testing conventional random access memories and how march test cannot guarantee higher defect coverage. The paper then motivates the need of development of special Design-for-Testability (DfT). A concept of a new DfT is then proposed. The concept is further exploited and mapped into two different DfT circuitries: (i) Short Write Time and (ii) Low Write Voltage. Both DfT schemes are implemented and simulated; the simulation results show that defects causing the RRAM cell to enter an undefined state are easily detected.

Among several types of emerging memory technologies, memristor-based nonvolatile resistive RAM (ReRAM) is currently being investigated as a promising candidate to potentially replace the popular Flash memories, and even other conventional memories such as SRAM and DRAM. At the architectural level, crossbar cell array structure is considered one of the best ways to implement memristor-based ReRAM. This chapter presents an overview of promising ReRAM technologies, their potential benefits, and the key research challenges, with a focus on reduction/oxidation (Redox)-based RAM. It briefly describes the basic operation principles of memristive memory cells, and presents the memristor-based crossbar memory architecture to finally focus on the serious negative impact of the current sneak-paths. Then, two possible methodologies are explored as means to deal with the sneak-path problem, concerning (i) novel storage cell structures, and (ii) modifications in the memory architecture. More specifically, (i) anti-parallel memristive switches are studied as potential cross-point elements in ReRAM arrays, in comparison with anti-serial (complementary) memristive switches. A comprehensive and comparative presentation between them is provided, while commenting on their overall performance and the most appropriate switching characteristics that the structural memristors should have, in order to better fit to memory applications. Moreover, (ii) five alternative architectures (topologies) for passive crossbar ReRAM are presented, which are based on the introduction of a certain percentage of insulating nodes spread out inside the array according to specific distribution patterns. Both approaches enable crossbar memory arrays without select devices, thus they simplify the array fabrication process and could be well-suited for future data storage applications. Finally, XbarSim, a GUI-based educational simulation tool aiming to serve students/researchers who wish to explore and study the memristive crossbar circuit architecture, is presented.

The traditional von Neumann architecture limits the increase in computing efficiency and results in massive power consumption in modern computers due to the separation of storage and processing units. The novel neuromorphic computation system, an in-memory computing architecture with low power consumption, is aimed to break the bottleneck and meet the needs of the next generation of artificial intelligence (AI) systems. Thus, it is urgent to find a memory technology to implement the neuromorphic computing nanosystem. Nowadays, the silicon-based flash memory dominates non-volatile memory market, however, it is facing challenging issues to achieve the requirements of future data storage device development due to the drawbacks, such as scaling issue, relatively slow operation speed, and high voltage for program/erase operations. The emerging resistive random-access memory (RRAM) has prompted extensive research as its simple two-terminal structure, including top electrode (TE) layer, bottom electrode (BE) layer, and an intermediate resistive switching (RS) layer. It can utilize a temporary and reversible dielectric breakdown to cause the RS phenomenon between the high resistance state (HRS) and the low resistance state (LRS). RRAM is expected to outperform conventional memory device with the advantages, notably its low-voltage operation, short programming time, great cyclic stability, and good scalability. Among the materials for RS layer, indium gallium zinc oxide (IGZO) has shown attractive prospects in abundance and high atomic diffusion property of oxygen atoms, transparency. Additionally, its electrical properties can be easily modulated by controlling the stoichiometric ratio of indium and gallium as well as oxygen potential in the sputter gas. Moreover, since the IGZO can be applied to both the thin-film transistor (TFT) channel and RS layer, it has a great potential for fully integrated transparent electronics application.In this work, we proposed amorphous transparent IGZO-based RRAMs and investigated switching behaviors of the memory cells prepared with different top electrodes. First, ITO was choosing to serve as both TE and BE to achieve high transmittance. A multi-target magnetron sputtering system was employed to deposit all three layers (TE, RS, BE layers) on glass substrate. I-V characteristics were evaluated by a semiconductor parameter analyzer, and the bipolar RS feature of our RRAM devices was demonstrated by typical butterfly curves. The optical transmission analysis was carried out via a UV-Vis spectrometer and the average transmittance was around 80% out of entire devices in the visible-light wavelength range, implying high transparency. We adjusted the oxygen partial pressure during the sputtering of IGZO to optimize the property because the oxygen vacancy concentration governs the RS performance. Electrode selection is crucial and can impact the performance of the whole device. Thus, Cu TE was chosen for our second type of device because the diffusion of Cu ions can be beneficial for the formation of the conductive filament (CF). A ~5 nm SiO2 barrier layer was employed between TE and RS layers to confine the diffusion of Cu into the RS layer. At the same time, this SiO2 inserting layer can provide an additional interfacial series resistance in the device to lower the off current, consequently, improve the on/off ratio and whole performance. Finally, an oxygen affinity metal Ti was selected as the TE for our third type of device because the concentration of the oxygen atoms can be shifted towards the Ti electrode, which provides an oxygengettering activity near the Ti metal. This process may in turn lead to the formation of a sub-stoichiometric region in the neighboring oxide that is believed to be the origin of better performance.In conclusion, the transparent amorphous IGZO-based RRAMs were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of RRAMs, we integrated a set of TE materials, and a barrier layer on IGZO-based RRAM and compared the switch characteristics. Our encouraging results clearly demonstrate that IGZO is a promising material in RRAM applications and breaking the bottleneck of current memory technologies.

In-Memory Computing (IMC) provides an alternative to conventional von-Neumann-based architectures by performing computation directly within memory, thus significantly reducing data movement. Resistance Random Access Memory (RRAM) crossbar array are explored for in-memory computing (IMC). A hybrid platform with bit-sliced MAC architecture and RRAM crossbar array is proposed here to perform in-memory computing. This paper presents a 4x4 PMO-based a RRAM crossbar array with an FPGA for controlling data flow and showing its utility for complete MAC operation. The RRAM array stores the data, while the FPGA sends the input signal and does the post-processing after the data passes through the RRAM array. Such architectures hold strong promise for ultra-low-power AI applications in wearables, edge sensing, and portable analytics.

The high demand for performance and energy efficiency poses significant challenges for computing systems in recent years. The memristor-based crossbar array architecture is enthusiastically regarded as a potential competitor to traditional solutions due to its low power consumption and fast switching speed. Especially by leveraging self-rectifying memristive devices, passive crossbar arrays potentially enable high memory densities. Nonetheless, due to the lack of a switching control per cell, these passive, self-rectifying memristive crossbar arrays (srMCA) suffer from sneak path current issues that limit the range of accurate operation of the crossbar array. In this work, the sneak path current issues in the passive srMCAs based on self-rectifying bipolar and complementary switching memristive devices are comparatively analyzed. Under consideration of the worst-case scenario, three reading schemes are investigated: one wordline pull-up (OneWLPU), all wordline pull-up (AllWLPU), and floating (FL) reading schemes. As a conclusion, despite different switching dynamics, both types of self-rectifying memristive devices can efficiently suppress sneak path current in the srMCAs. In the FL reading scheme, the sneak path current flowing through the unselected reversely biased memristive cells in the srMCA can be considered as an accurate estimation for the practical sneak path current in the srMCA. By analyzing the sneak path current in the srMCAs with a size up to 64 × 64, it is demonstrated that the leakage current plays a crucial role for suppressing the sneak path current, and the sneak path current via an individual cell exhibits a continuous decrease while the accumulated total sneak path current in the unselected reverse biased region is increasing with expanding the crossbar size. The comparative study on the bipolar and complementary memristive devices based srMCAs under diverse reading schemes reveals the influence of the switching dynamics on the sneak path current effect in the srMCAs, and provides a beneficial reference and feasible solutions for the future optimization of the crossbar topology with the intention of mitigating sneak path effects.

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay.

DQN based page allocation for ReRAM main memory

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360x and the energy consumption by ~895x, across the evaluated machine learning benchmarks.