An Efficient Register Renaming Technique with Delayed Allocation and Register Packing

Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors

Modern processors have large instruction windows to improve performance. They usually adopt register renaming, where every active instruction with a valid destination needs a physical register. As the instruction windows get larger, however, bigger physical register files are required. To solve this problem, we proposed a physical register sharing technique. It shares a physical register among multiple instructions based on a value similarity. As a result, we achieved performance improvement without increasing the size of the physical register file. In addition, the proposed technique can also be used to reduce the timing, complexity and area overhead of the physical register file.

Runahead execution improves processor performance by accurately prefetching long-latency memory accesses. When a long-latency load causes the instruction window to fill up and halt the pipeline, the processor enters runahead mode and keeps speculatively executing code to trigger accurate prefetches. A recent improvement tracks the chain of instructions that leads to the long-latency load, stores it in a runahead buffer, and executes only this chain during runahead execution, with the purpose of generating more prefetch requests. Unfortunately, all prior runahead proposals have shortcomings that limit performance and energy efficiency because they release processor state when entering runahead mode and then need to refill the pipeline to restart normal operation. Moreover, runahead buffer limits prefetch coverage by tracking only a single chain of instructions that leads to the same long-latency load. We propose precise runahead execution (PRE) which builds on the key observation that when entering runahead mode, the processor has enough issue queue and physical register file resources to speculatively execute instructions. This mitigates the need to release and re-fill processor state in the ROB, issue queue, and physical register file. In addition, PRE pre-executes only those instructions in runahead mode that lead to full-window stalls, using a novel register renaming mechanism to quickly free physical registers in runahead mode, further improving efficiency and effectiveness. Finally, PRE optionally buffers decoded runahead micro-ops in the frontend to save energy. Our experimental evaluation using a set of memory-intensive applications shows that PRE achieves an additional 18.2% performance improvement over the recent runahead proposals while at the same time reducing energy consumption by 6.8%.

Recent work in the field of value prediction (VP) has shown that given an efficient confidence estimation mechanism, prediction validation could be removed from the out-of-order engine and delayed until commit time. As a result, a simple recovery mechanism—pipeline squashing—can be used, whereas the out-of-order engine remains mostly unmodified. Yet, VP and validation at commit time require additional ports on the physical register file, potentially rendering the overall number of ports unbearable. Fortunately, VP also implies that many single-cycle ALU instructions have their operands predicted in the front-end and can be executed in-place, in-order. Similarly, the execution of single-cycle instructions whose result has been predicted can be delayed until commit time since predictions are validated at commit time. Consequently, a significant number of instructions—10% to 70% in our experiments—can bypass the out-of-order engine, allowing for a reduction of the issue width. This reduction paves the way for a truly practical implementation of VP. Furthermore, since VP in itself usually increases performance, our resulting {Early—Out-of-Order—Late} Execution architecture, EOLE, is often more efficient than a baseline VP-augmented 6-issue superscalar while having a significantly narrower 4-issue out-of-order engine.

Value prediction improves instruction level parallelism in superscalar processors by breaking true data dependencies. Although this technique can significantly improve overall performance, most of the state-of-the-art value prediction approaches require high hardware cost, which is the main obstacle for its wide adoption in current processors. To tackle this issue, we revisit load value prediction as an efficient alternative to the classical approaches that predict all instructions. By speculating only on loads, the pressure over shared resources (e.g., the Physical Register File) and the predictor size can be substantially reduced (e.g., more than 90% reduction compared to recent works). We observe that existing value predictors cannot achieve very high performance when speculating only on load instructions. To solve this problem, we propose a new, accurate and low-cost mechanism for predicting the values of load instructions: the Address-first Value-next Predictor with Value Prefetching (AVPP). The key idea of our predictor is to predict the load address first (which, we find, is much more predictable than the value) and to use a small non-speculative Value Table (VT)—indexed by the predicted address—to predict the value next. To increase the coverage of AVPP, we aim to increase the hit rate of the VT by predicting also the load address of a future instance of the same load instruction and prefetching its value in the VT. We show that AVPP is relatively easy to implement, requiring only 2.5% of the area of a 32KB L1 data cache. We compare our mechanism with five state-of-the-art value prediction techniques, evaluated within the context of load value prediction, in a relatively narrow out-of-order processor. On average, our AVPP predictor achieves 11.2% speedup and 3.7% of energy savings over the baseline processor, outperforming all the state-of-the-art predictors in 16 of the 23 benchmarks we evaluate. We evaluate AVPP implemented together with different prefetching techniques, showing additive performance gains (20% average speedup). In addition, we propose a new taxonomy to classify different value predictor policies regarding predictor update, predictor availability, and in-flight pending updates. We evaluate these policies in detail.

The majority of register file designs follow one of two well-known approaches.Manymodern high-performance processors (POWER4 [1], Pentium4 [2]) use a merged register file that holds both architectural and rename registers. Other processors use a Future File (eg, Opteron [3]) with rename registers kept separately in reservation stations. Both approaches have issues that may limit their application in futuremicroprocessors. The merged register file scales poorly in terms of powerperformance while the Future File has to pay a large penalty due on branch mis-prediction recovery. In addition, the Future File requires the use of the less scalable mechanism of reservation stations. This paper proposes to combine the best aspects of the traditional Future File architecture with those of the merged physical register file. The key point is that the new architecture separates the processor state, in particular the registers, and the execution units in the pipeline back-end. Therefore it is called Decoupled State-Execute Architecture. The resulting register file can be accessed in the pipeline front-end and has several desirable properties that allow efficient application of several optimizations, most notably the register file banking and a novel writeback filtering mechanism. As a result, only a 1.0% IPC degradation was observed with aggressive banking and the energy consumption was lowered by the new writeback filtering technique. Together, the two optimizations remove approximately 80% of the energy consumed in register file data array.

Soft errors caused by cosmic rays or alpha particles emitted from the packaging material around the chips are becoming an increasingly important challenge in reliable microprocessor design. Transistor density, and die size trends show that soft errors will gain even more importance in the future. Due to their significant overheads, most redundancy schemes are employed where the penalty incurred can be hidden in the pipeline. Most contemporary processors employ a large physical register file to hold the produced results which may reside there for a long time. The register file is a critical element of a microprocessor and is needed to be protected against soft errors. In this paper we propose an SRAM bitcell design with ability to hold a redundant copy of the data and compare the copies with built-in comparators to detect a possible mismatch. Our experimental results show that the proposed design has 34% area, 7.9% power 2% delay overheads which are further reducible and can protect the register file against Silent Data Corruption (SDC).

High-performance microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a large number of cycles after the result generation. We observed that a significant fraction (about 45%) of the result values are never read from the register file and are not required to recover from branch mispredictions. In this paper, we propose SPARTAN - a set of micro-architectural extensions that predicts such transient values and in many cases completely avoids physical register allocations to them. We show that the transient values can be predicted as such with more than 97% accuracy on the average across simulated SPEC 2000 benchmarks. We evaluate the performance of SPARTAN on a variety of configurations and show that significant improvements in performance and energy-efficiency can be realized. Furthermore, we directly compare SPARTAN against a number of previously proposed schemes for register optimizations and show that our technique significantly outperforms all those schemes.

An ADC with a sampling rate of tens of GS/s and a high input bandwidth can greatly ease the design of wireless network systems. Such ADCs help in simplifying the analog front end design by relaxing the requirements for anti-alias and anti-image filtering. Having a bandwidth of up to 7.2GHz facilitates direct sampling on the 5G full FR1 band including LTE-U and WiFi 6/7 networks. However, the available state-of-the-art high-speed ADCs operating at 20GS/s or higher are designed mostly for wireline communications [5] and are not suitable for wireless base station applications where a high spectral dynamic range with an NSD of -147dBFS/Hz and an SFDR of 70dB are required to support 1024-QAM and higher modulations. The other high-resolution ADCs available in the range from 5-20GS/s [1–4] have higher power consumption, larger area and insufficient SFDR to be reliably used in the previously mentioned applications. The reported ADC achieves 24GS/s sampling rate with an input bandwidth of 7.2GHz as well as 76dB SFDR and -147.5dBFS/Hz NSD with high power efficiency and small area.

As the technology scales down, the increased power density brings in significant system reliability issues. Therefore, the temperature monitoring and the induced power management become more and more critical. The thermal fluctuation effects of the recently discovered spintronic memristor make it a promising candidate as a temperature sensing device. In this paper, we carefully analyzed the thermal fluctuations of spintronic memristor and the corresponding design considerations. On top of it, we proposed a temperature sensing circuit design by combining spintronic memristor with the traditional CMOS current reference. Our simulation results show that the proposed design can provide high accuracy of temperature detection within a much smaller footprint compared to the traditional CMOS temperature sensor designs. As magnetic device scales down, the relatively high power consumption is expected to be reduced.

Research on Pipe Network Transformation of Central Heating System Based on Adjustable Jet Pump Technology

One of the concepts currently pursued to provide the ideal network architecture for supporting the next generation Internet consists of transmitting the Internet protocol (IP) packets directly over the wavelength division multiplexing (WDM) layer of extant optical networks. The challenge of this concept is to make the optical bandwidth directly accessible to IP with the statistical multiplexing necessary to support the bursty nature of IP traffic in a cost effective way. This paper proposes the multi-token inter-arrival (MTIT) access protocol designed to achieve a bandwidth efficient multiplexing technique in WDM ring networks. The network throughput is maximized without violating the desired access delay requirement by controlling the inter-arrival time as opposed to controlling the rotation time as proposed in existing standards, e.g., FDDI. It is shown that the MTIT protocol efficiency grows with the number of wavelengths-in full agreement with the WDM technology trend-and does not depend on the packet length-a feature ideal for IP implementation. In addition, the protocol provides a unique token control technique that allows to maintain the channel access delay at a node bounded even within the round trip propagation of a ring.

The conventional CMOS analog multiplier circuits used in different architectures suffer from linearity problems, low processing speed, low accuracy large on-chip area and high power consumption. One of the possible solution to overcome these problems is to use memristive components in analog multiplier design. This paper proposes a CMOS analog multiplier design with memristive components. The aim of the paper is to compare the power consumption and overall characteristic of the memristor-based multiplier with the performance conventional CMOS multiplier circuit. The circuit is designed using TSMC 180nm CMOS technology, and the simulations are conducted in SPICE. The effects of channel modulation and temperature on the multiplier performance are discussed.

Applications like spectrum sensing, radar signal processing, and pattern matching by convolving a signal with a long code, as in GPS, require large FFT sizes. ASIC implementations of such FFTs are challenging due to their large silicon area and high power consumption. However, the signals in these applications are sparse, i.e., the energy at the output of the FFT/IFFT is concentrated at a limited number of frequencies and with zero/negligible energy at most frequencies. Recent advances in signal processing have shown that, for such sparse signals, a new algorithm called the sparse FFT (sFFT) can compute the Fourier transform more efficiently than traditional FFTs [1].

Flexible router architecture for network-on-chip