AVPP

The newly emerging many-core-on-a-chip designs have renewed an intense interest in parallel processing. By applying Amdahl's formulation to the programs in the PARSEC and SPLASH-2 benchmark suites, we find that most applications may not have sufficient parallelism to efficiently utilize modern parallel machines. The long sequential portions in these application programs are caused by computation as well as communication latency. However, value prediction techniques may allow the ldquoparallelizationrdquo of the sequential portion by predicting values before they are produced. In conventional superscalar architectures, the computation latency dominates the sequential sections. Thus, value prediction techniques may be used to predict the computation result before it is produced. In many-core architectures, since the communication latency increases with the number of cores, value prediction techniques may be used to reduce both the communication and computation latency. In this paper, we extend Amdahl's formulation to model the data redundancy inherent to each benchmark, thereby identifying the potential of value prediction techniques. Our analysis shows that the performance of PARSEC benchmarks may improve by a factor of 180 and 230 percent for the SPLASH-2 suite, compared to when only the intrinsic parallelism is considered. This demonstrates the immense potential of fine-grained value prediction in reducing the communication latency in many-core architectures.

Physical register file in processors needs to provide more registers when the issue width and pipeline stages increase. Expansion of the physical register file results in long access delay, larger area, and high-power consumption, which needs carefully considerations in superscalar processor design. This article designs an efficient register-renaming technique. It adopts delayed allocation and register packing techniques to improve the efficiency of physical register files temporally and spatially. Experimental results on BOOMv2 show that when the physical register file contains only 34 registers, this technology can improve the performance by 3.59-4.46 times, which achieves the peak performance with more than 64 physical registers.

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar architectures. Instructions to be executed simultaneously are statically scheduled by a compiler like VLIW architectures. Therefore, parallelism derivation and instruction scheduling are very important for Jetpipeline. Software pipelining is one of the well-known techniques to achieve high throughput when processing loop programs. In this paper, we propose software pipelining for Jetpipeline. Firstly, the overview of the Jetpipeline architecture is described. Then the banked register configuration of Jetpipeline for reducing hardware complexity and supporting software pipelining is presented. Finally, the effectiveness of software pipelining for Jetpipeline is discussed by simulation. >

Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors

Trace reuse is an effective way of improving the performance of superscalar processors by skipping the execution of a sequence of instructions with known input and output values. However, the extra hardware complexity is of special concern when implementing such mechanisms. In this paper, we describe ways to reduce these requirements for Reuse through Speculation on Traces (RST). RST combines instruction and trace reuse with value prediction in an integrated mechanism to provide missing trace inputs when execution reaches the beginning of a trace. Speculatively reused traces do not consume resources in the execution pipeline, as they are not executed. In this paper, we study the effects of constraining reuse tables to effectively reduce the number of reuse candidates and comparisons. We compare our approach to instruction reuse, trace reuse and value prediction. We show that RST reuses more instructions and has better performance than traditional trace reuse, with an average speedup over a baseline without reuse of 1.21.

Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity in multicore processors. Based on this study, we propose a prefetching module located in the llc which uses two small tables, and where the computational complexity of which is linear with the number of computing threads. Our Markov-based technique is able to keep track and make clustering of several simultaneous groups of memory accesses coming from multiple simultaneous threads in a multicore processor. It can quickly identify complex address groups and trigger prefetch with very high accuracy. Our simulations show an improvement of up to 76% in the hit ratio of an off-chip dram cache for multicore architecture over the conventional prefetch technique (g/dc). Also, the overhead of prefetch requests (failed prefetches) is reduced by 48% in single core simulations and by 83% in multicore simulations.

Superscalar processors contain complex control logic in order to extract sufficient instruction level parallelism (ILP). The issue logic is one of the main sources of power dissipation in current superscalar processors. It has been estimated that up to 30% of the energy consumed by a processor is in the issue logic. This paper presents a novel compiler assisted approach to power reduction where we use compiler analysis to pass information to the processor about the number of entries needed, allowing the processor to resize the issue queue dynamically which limit the number of instruction dispatched and resident in the queue reduces the energy consumption without adversely affecting performance. Compared with hardware scheme, our approach is simpler faster and saves more energy. Using the approach we achieve 43.3% dynamic and 28.5% static power savings.

Data dependencies have become one of the main bottlenecks of current superscalar processors. Data speculation is gaining popularity as a mechanism to avoid the ordering imposed by data dependencies. Loads and stores are very good candidates for data speculation since their effective address has a regular behavior and then, they are highly predictable. In this paper we propose a mechanism called Address Prediction and Data Prefetching that allows load instructions to obtain their data at the decode stage. Besides, the effective address of load and store instructions is also predicted. These instructions and those dependent on them are speculatively executed. The technique has been evaluated for an out-of-order processor with a realistic configuration. The performance gain is about 19% in average and it is much higher for some benchmarks (up to 35%).

Improving the performance of embedded systems can be supported by increasing the hit rates of last level caches (LLC). To enhance the hit rates of LLC, we propose a new prefetch technique. The proposed prefetch technique can fetch the data from main memory prior to actual requests to reduce the long latency to the main memory. To support the proposed technique, we introduce a new structure, LLC buffer which contains several memory blocks nearby the previous referenced memory block. In case that the LLC capacity is not enough, the proposed prefetch technique can improve the performance of embedded systems significantly.

An integrated, hardware/software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targeted, the overall approach is applicable to other CISC ISAs. To provide high performance on frequently executed code sequences, fully transparent dynamic translation software decomposes CISC superblocks into RISC-style micro-ops. Then, pairs of dependent micro-ops are reordered and fused into macro-ops held in a large, concealed code cache. The macro-ops are fetched from the code cache and processed throughout the pipeline as single units. Consequently, instruction level communication and management are reduced, and processor resources such as the issue buffer and register file ports are better utilized. Moreover, fused instructions lead naturally to pipelined instruction scheduling (issue) logic, and collapsed 3-1 ALUs can be used, resulting in much simplified result forwarding logic. Steady state performance is evaluated for the SPEC2000 benchmarks, and a proposed x86 implementation with complexity similar to a two-wide superscalar processor is shown to provide performance (instructions per cycle) that is equivalent to a conventional four-wide superscalar processor.

UItraSpare I is a second-generation superscalar processor. It is a high performance, highly integrated, four issue superscalar processor based on the Spare Version 9 64-bit RISC architecture. We have extended the core instruction set to include graphics instructions that provide the most common operations related to two dimensional image processing; two- and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit components. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multimedia applications.

In Speculative Multithreading, data dependence that limits the speedup of speculative parallelization needs to be resolved to achieve a high performance. This paper designs a synchronization execution model, with the support of compiler, to synchronize store and load instructions that frequently have data dependence on each other. We use hardware profiler to gather dependence violation information of memory data, and the profiler information is fed back to the compiler. The compiler analyzes the synchronization efficiency, select store/load pairs of great synchronization potential, and inserts synchronization instructions using insertion algorithm. Loop threads and non-loop threads can both be synchronized. The hardware support is also given in the paper. The experimental results show that the synchronization under the compiler support can effectively resolve some memory data dependence and improve the performance of the speculative execution.

The first commercial sales of fuel cell automobiles based on high-performance proton exchange membrane fuel cells (PEMFCs) mark an important milestone for the field, bringing to the market a zero-emission vehicle with the advantages of long driving range and short refuelling time.1 Chiefly due to the use of Pt electrocatalysts in PEMFCs, they are not yet cost competitive with gasoline engines. Thus, further cost reductions are needed to facilitate PEMFCs’ wider adoption. Current efforts have been focused on the reduction of the Pt loading in membrane electrode assemblies (MEAs), however, the acidic environment has been a significant barrier.2 A fundamentally different approach to lower the cost of fuel cells is to switch from the acidic proton exchange membranes (PEMs) to the alkaline hydroxide exchange membranes (HEMs) in HEM fuel cells (HEMFCs), which could enable the employment of platinum-group-metal (PGM)-free anode and cathode catalysts.3 , 4 A key challenge in the development of high performance HEMFCs is the lack of chemically stable, ionically conductive, and mechanically robust HEMs. HEMs are typically composed of organic cations tethered to a polymer backbone, with the charge balanced by free OH− anions. The alkaline stability of both the organic cation and the polymer backbone limit the overall stability of the HEM.5 Recently, Marino and Kreuer reported that piperidinium exhibited a 21-fold increase in alkaline stability as compared to benzyl trimethyl ammonium, the benchmark ammonium.6 Meanwhile, a reliable and scalable synthetic route to tether piperidinium to a stable polymer backbone remains elusive. It is generally accepted that functionalized ether-bond-containing engineering plastics, e.g., poly(arylene ether) and poly(phenylene oxide), are susceptible to chemical degradation via ether-bond scission and the subsequent decomposition.7 Another key challenge in the development of HEMs is the tradeoff between ionic conductivity and mechanical strength. In this work, we report a new family of poly(aryl piperidinium) (PAP) HEMs/HEIs in which alkaline stable piperidinium cations were tethered to an ether-bond-free, rigid and hydrophobic aryl backbone. PAP’s excellent properties originate from the combination of the stable piperidinium cation and the rigid ether-bond-free aryl backbone which enables an unprecedented combination of a high ion exchange capacity (IEC) and a low water uptake/swelling ratio. PAP HEMs have demonstrated excellent alkaline stability (e.g., no degradation in 1 M KOH for 2000 h at 100 °C), high OH− conductivity (e.g., 200 mS cm−1 at 95 °C in water), and high mechanical strength (140 MPa). PAP also has the selective solubility to make ionomer solutions and can be cast into membranes with thicknesses down to 5 µm. MEAs using PAP HEM and the corresponding ionomer showed a peak power density of 860 mW cm−2 at 95 °C with minimal optimization. Further, discharge at 90 °C revealed no voltage degradation at constant current density of 200 mA cm−2 for 60 h, in contrast to the rapid degradation of a commercial membrane/ionomer under identical conditions (within minutes). (1) Yoshida, T.; Kojima, K. Electrochem Soc Inte 2015, 24, 45. (2) Setzler, B. P.; Zhuang, Z. B.; Wittkopf, J. A.; Yan, Y. S. Nat Nanotechnol 2016, 11, 1020. (3) Varcoe, J. R.; Slade, R. C. T. Fuel Cells 2005, 5, 187. (4) Dekel, D. R. J Power Sources 2017. (5) Varcoe, J. R.; Atanassov, P.; Dekel, D. R.; Herring, A. M.; Hickner, M. A.; Kohl, P. A.; Kucernak, A. R.; Mustain, W. E.; Nijmeijer, K.; Scott, K.; Xu, T. W.; Zhuang, L. Energ Environ Sci 2014, 7, 3135. (6) Marino, M. G.; Kreuer, K. D. Chemsuschem 2015, 8, 513. (7) Arges, C. G.; Ramani, V. P Natl Acad Sci USA 2013, 110, 2490.

Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.

Serialization of threads due to critical sections is a fundamental bottleneck to achieving high performance in multithreaded programs. Dynamically, such serialization may be unnecessary because these critical sections could have safely executed concurrently without locks. Current processors cannot fully exploit such parallelism because they do not have mechanisms to dynamically detect such false inter-thread dependences. We propose Speculative Lock Elision (SLE), a novel micro-architectural technique to remove dynamically unnecessary lock-induced serialization and enable highly concurrent multithreaded execution. The key insight is that locks do not always have to be acquired for a correct execution. Synchronization instructions are predicted as being unnecessary and elided. This allows multiple threads to concurrently execute critical sections protected by the same lock. Misspeculation due to inter-thread data conflicts is detected using existing cache mechanisms and rollback is used for recovery. Successful speculative elision is validated and committed without acquiring the lock. SLE can be implemented entirely in microarchitecture without instruction set support and without system-level modifications, is transparent to programmers, and requires only trivial additional hardware support. SLE can provide programmers a fast path to writing correct high-performance multithreaded programs.