An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they will be able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS?89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design.

This paper introduces a best approach for Least Significant Bit (LSB) based on image steganography that enhances the existing LSB substitution techniques to improve the security level of hidden information. It is a new approach to substitute LSB of RGB true color image. The new security conception hides secret information within the LSB of image where a secret key encrypts the hidden information to protect it from unauthorized users. In general, in LSB methods, hidden information is stored into a specific position of LSB of image. For this reason, knowing the retrieval methods, anyone can extract the hidden information. In our paper, hidden information is stored into different position of LSB of image depending on the secret key. As a result, it is difficult to extract the hidden information knowing the retrieval methods. We have used the Peak Signal-to-Noise Ratio (PSNR) to measure the quality of the stego images. The value of PSNR gives better result because our proposed method changes very small number of bits of the image. The obtained results show that the proposed method results in LSB based image steganography using secret key which provides good security issue and PSNR value than general LSB based image steganography methods.

Adversarial attacks on Neural Network weights, such as the progressive bit-flip attack (PBFA), can cause a catastrophic degradation in accuracy by flipping a very small number of bits. Furthermore, PBFA can be conducted at run time on the weights stored in DRAM main memory. In this work, we propose RADAR, a Run-time adversarial weight Attack Detection and Accuracy Recovery scheme to protect DNN weights against PBFA. We organize weights that are interspersed in a layer into groups and employ a checksum-based algorithm on weights to derive a 2-bit signature for each group. At run time, the 2-bit signature is computed and compared with the securely stored golden signature to detect the bit-flip attacks in a group. After successful detection, we zero out all the weights in a group to mitigate the accuracy drop caused by malicious bit-flips. The proposed scheme is embedded in the inference computation stage. For the ResNet-18 ImageNet model, our method can detect 9.6 bit-flips out of 10 on average. For this model, the proposed accuracy recovery scheme can restore the accuracy from below 1% caused by 10 bit flips to above 69%. The proposed method has extremely low time and storage overhead. System-level simulation on gem5 shows that RADAR only adds <1% to the inference time, making this scheme highly suitable for run-time attack detection and mitigation.

To enhance the payload of secret data a scheme on the basis of least significant bit (LSB) substitution cascaded with pixel value differencing (PVD) has been proposed in this paper. Firstly secret bits are embedded using PVD method where smooth areas obtain small number of bits and higher bits in the edged area. Then bits are also embedded in the same pixel block by applying LSB replacement method as a cascading manner. The technique ensures more hiding capacity along with security as two methods are applied as cascaded manner on the same pixel block. Experimental result shows that proposed method can hide nearly double amount of secret data, compared to PVD method with good visual quality of stego-images.

Network-on-Chip (NoC) links consume a significant fraction of the total NoC power. We present Selective Packet Interleaving (SPI), a flit transmission scheme that reduces power consumption in NoC links. SPI decreases the number of bit transitions in the links by exploiting the multiplicity of virtual channels in a NoC router. SPI multiplexes flits to the router's output link so as to minimize the number of bit transitions from the previously transmitted flit. Analysis and simulations demonstrate a reduction of up to 55% in the number of bit transitions and up to 40% savings in power consumed on the link. SPI benefits grow with the number of virtual channels. SPI works better for links with a small number of bits in parallel. While SPI compares favorably against bus inversion, combining both schemes helps to further reduce bit transitions.

In this paper, we propose a new test data compression method for reducing test data volume and test application time. The proposed method consists of two steps: scan chain compaction and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The compacted scan chain is partitioned to the multiple internal scan chains for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression method delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the ISCAS-89 test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

Exhaustive self-testing of combinational circuitry within the framework of the level-sensitive scan design (LSSD) discipline requires that every output node depend on a small number of input nodes. We present here efficient algorithms that take an arbitrary block of combinational logic and add to it the smallest number of bits of new LSSD registers necessary to: (1) partition the logic so that no output depends on more thank inputs, and (2) maintain timing within the block (so that all input-to-output paths encounter the same number of bits of register). Our partitioning algorithms conform to two different design constraints. We also show that the unconstrained partitioning problem is NP-complete.

The testing of System on Chip (SoC) components in Very-Large-Scale Integrated Circuits (VLSI) presents significant challenges due to excessive power dissipation and data volume. The inherent complexity of VLSI circuits, which integrate numerous transistors on a single silicon substrate, increases fault likelihood, leading to large data volumes and longer test times. The conventional scan chain-based testing in Design-for-Testability (DFT), result in high switching activity and power consumption, especially during shift operations. Addressing low power dissipation during testing is essential for chip durability, performance, cost, and reliability. Otherwise, the chip may foresee power surge, voltage drops, hotspots, thermal stress, false timing failures and mismatches due to the reason that test power is always double than the Functional power. Thus, in this paper, a new architecture based on Linear-Feedback Shift-Register (LFSRs) driven architecture that is analogous to that of the traditional scan is proposed, to help diminish transition count in turn decreasing power usage in the testmode. The architecture employs Power gating and Automatic test pattern generation (ATPG) filling methods in the contribution of ensuring the design is in a low power state that provides a high level of test coverage at the lowest switching activity. The experimentation is tested on ISCAS89 benchmarking circuits, and on hyper convoluted industrial designs with Cadence Genus and Modus tools. Scalability between small benchmark circuits and large industrial designs is confirmed by performance analysis of a wide range of circuit complexities. Experimental data demonstrates that LFSR-based method showed a significant 1.34X decrease in the toggling activity, as well as impressive 4-10K decreasing pattern and an overall acceleration of the runtime of approximately 1-1.5 hours over the scan-based designs. Test coverage is enhanced 2.97-3.76 with the case of the static test, 6.03-7.51 with the case of the delay test and 0.41-0.59 with the case of scan tests. Test power recorded a decline of about 40-47 on industrial design exhibiting its substantial findings on intricate designs.

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment. Meanwhile, our paper also introduces a novel algorithm of scan-block clustering. The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding. Thus, it can significantly reduce the test power and test data volume. Experimental results using Mintest test set on the larger ISCAS'89 benchmarks show that the proposed method reduces the switching activity significantly by 72%–94% and provides a best possible test compression of 74%–94% with little hardware overhead.

The paper proposes a Scan Chain Adaptation Through ECO (SCATE) methodology to accommodate scan chain changes at advanced physical design stage into the existing DFT compression logic and eliminates the need of re-running the complete scan insertion flow. With the proposed methodology scan chain changes can be implemented as ECO to achieve cycle time reduction with minimum overhead. It can handle last minute changes due to the addition of new scan chains or changes in scan chain lengths in existing IPs. The scope of the work is also extended to reduce the cycle time of a derivative product from a base design. Results from industrial designs in 28FDSOI and 40nm CMOS technologies show SOC test coverage of above 99% when new scan chains were included using the proposed methods. Test time gain of more than 30% was observed by adjusting the maximum scan chain lengths. Use of SCATE methodology enabled DFT modifications through ECO and saved design cycle time by avoiding loopback to fresh DFT insertion, Timing analysis and Physical design flows in industrial SOCs

&lt;p&gt;Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.&lt;/p&gt; &lt;p&gt;At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.&lt;/p&gt; &lt;p&gt;We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.&lt;/p&gt; &lt;p&gt;In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced&lt;/p&gt; &lt;p&gt;by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.&lt;/p&gt;

Based on digitized TV frames a computer simulation study was conducted on a motion -adaptive TV data compression scheme, defined as one in which a 2- dimensional transformapplied to subblocks is followed by the transmission to the receiving site of only changedsubblocks. Performance was measured both by calculation of Normalized Mean Square Errorand by subjective viewing of reconstructed frames. Two systems designs leading to 512x512resolution operation (one based on the Hadamard and one on the Discrete Cosine Transform)were prepared.IntroductionThe motion -adaptive TV data compression described herein is more effective than conven-tional intraframe techniques because it encompasses them and furthermore takes advantageof the correlation between frames by updating only those subblocks which have changed.Following a 2 -D transform performed on small (e.g. 8x8) subblocks, intraframe compressionis achieved by assigning a small number of bits (or none) to each transform coefficient.This bit allocation is made adaptive by assigning fewer bits to those subblocks within aframe which exhibit less busyness or activity. Next, motion -adaptivity, a form of inter -frame compression, is provided by having the amount of change in coefficients between thecurrent subblock and the corresponding subblock of the previous frame determine which trans-form subblocks to transmit. This process has been simulated and an approach to hardwareimplementation derived.BackgroundTwo -dimensional transforms combined with frame to frame motion -adaptivity achieve highcompression ratios because they exploit pixel correlation in all three dimensions.