Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip

Network-on-Chip (NoC) is a popular communication and interconnection structure for multi or many-core system-on-chip (SoC). It mainly consists of routers, network interfaces and communication links. It typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple packet flits to share NoC communication links. DAMQ (Dynamically Allocation Multi Queues) based VC organization has higher buffer utilization but it also has a few problems. We present a novel NoC router architecture that provides solutions to these problems. It utilizes dynamic VC based buffering and index based arbitration methodologies. Arbitration is a critical operation employed in NoC routers that may results in lower speed, weak fairness, and difficulties in pipelining. Our arbitration techniques used in the presented router architecture overcome these problems. We have simulated and implemented our 2D-mesh NoC router using System-Verilog. The experimental results confirm the efficiency of our proposed NoC router in terms of superior router power and ASIC area as well as its operating speed. Performance metrics for different NoC configurations are determined and evaluated for a variety of traffic patterns.

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss.

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

In the movement from a multi‐core to a many‐core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network‐on‐chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many‐core chips. As the dimensions of mesh‐based NoC increase, routers and links serve as a major part to achieve the desired performance and low‐latency communication between cores. In this study, the authors propose an arbitration mechanism for NoC that leads to a reduction in congestion delay in routers as well as the network latency. The proposed mechanism is compatible with the bypass and baseline pipeline in routers. System simulations with Noxim demonstrate reduction in latencies and power consumption using different routing algorithms for 4×4,8×8 and 16×16 mesh topologies, as compared with a baseline router.

High throughput and low latency are the desirable characteristics of a multi processing system. CLICHE (ChipLevel Integration of Communicating Heterogeneous Elements) is the simplest form of Network-on-Chip architecture in terms of the layout and the local interconnections between resources and switches. The throughput varies with the number of virtual channels. When the number of virtual channels is increased, the throughput is increased. On the other hand, the average message latency increases with the number of virtual channels. To keep the latency low while preserving the throughput, the number of virtual channels is constrained to certain number. A novel multichannel signal acquisition module is proposed to integrate IP blocks. The proposed module achieves the optimal solution for large number of virtual channels. It reduces the memory requirement and power consumption as well. A Field Programmable Gate Arrays-based prototype is developed to verify the proposed module. Different case studies are studied in this research. As a result, the proposed module can schedule given tasks that are not schedulable via round-robin technique. Even in scenarios that both round-robin and proposed module can successfully schedule the given task, proposed module reduces the amount of data being acquired by 59%, which in turn decreases memory requirements and power consumption as well.

Simulation environment for link energy estimation in networks-on-chip with virtual channels

Exhaustive self-testing of combinational circuitry within the framework of the level-sensitive scan design (LSSD) discipline requires that every output node depend on a small number of input nodes. We present here efficient algorithms that take an arbitrary block of combinational logic and add to it the smallest number of bits of new LSSD registers necessary to: (1) partition the logic so that no output depends on more thank inputs, and (2) maintain timing within the block (so that all input-to-output paths encounter the same number of bits of register). Our partitioning algorithms conform to two different design constraints. We also show that the unconstrained partitioning problem is NP-complete.

Network on chip (NoC) is a design space covered by the manifold combinations of network topology options, routing algorithms, switch architectures, fault tolerant mechanisms and so on. In NoC structures, switches and links are important components on network layers and the effect of faults on links and switches in NoC leads to disturbance in internal communication and low reliability. The performance reduction of many-core NoC architectures depend strongly on the number of faulty switches. This bottleneck motivates us to propose a fault tolerant switch in which the ring roads help the switch to tolerate the faulty ports and also faulty cores. In the proposed scheme, switch ports are connected via redundant ring roads and so the connection with adjacent nodes is not limited to one port. Moreover, if the switch core is defected, the node stays active and cooperates in packet forwarding process. The main advantages of the proposed scheme are tolerating the permanent faults on core and ports of a switch and handling the input traffic of a faulty switch by preventing the congestion around the faulty region. The simulation results verify the robustness of the proposed intelligent switch against various kinds of permanent faults in NoC architectures.

With the development of integrated circuit technology, the NoC(Network-on-Chip) has become a research hotspot in recent years. In this paper, we analyze the relevant theories of NoC, especially about the NoC router, as it plays a very important role for connecting the network. We design a low latency NoC router based on the wormhole virtual channel switching, and implement it on RTL (Register Transfer Level). In addition, a two clock-cycles pipelined design pattern is used to improve the efficiency of the router. Finally, we use the “testbench” to test the router's functions with different input signals. The development tool is ISE provided by the company of Xilinx, and combined with Modelsim for waveform simulation.

Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard NoC system, only a fraction of power dissipation occurs due to static/leakage, while the rest is due to dynamic power. Dynamic dissipation includes self-switching and coupling switching dissipations, with the latter accounting for a significant part of total power dissipated. Several coding methods exist to minimize this dynamic power dissipation in NoC links. In this paper, we propose Algorithm 1 to reduce self-switching transitions and Algorithm 2 & 3 to lower coupling switching transitions in between the serial links, with Encoder/decoder modules placed at Network-Interface(NI) level. Simulations done on Xilinx Vivado design suite showed a maximum reduction of 64% in coupling switching activity compared to existing schemes.

Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.

Based on digitized TV frames a computer simulation study was conducted on a motion -adaptive TV data compression scheme, defined as one in which a 2- dimensional transformapplied to subblocks is followed by the transmission to the receiving site of only changedsubblocks. Performance was measured both by calculation of Normalized Mean Square Errorand by subjective viewing of reconstructed frames. Two systems designs leading to 512x512resolution operation (one based on the Hadamard and one on the Discrete Cosine Transform)were prepared.IntroductionThe motion -adaptive TV data compression described herein is more effective than conven-tional intraframe techniques because it encompasses them and furthermore takes advantageof the correlation between frames by updating only those subblocks which have changed.Following a 2 -D transform performed on small (e.g. 8x8) subblocks, intraframe compressionis achieved by assigning a small number of bits (or none) to each transform coefficient.This bit allocation is made adaptive by assigning fewer bits to those subblocks within aframe which exhibit less busyness or activity. Next, motion -adaptivity, a form of inter -frame compression, is provided by having the amount of change in coefficients between thecurrent subblock and the corresponding subblock of the previous frame determine which trans-form subblocks to transmit. This process has been simulated and an approach to hardwareimplementation derived.BackgroundTwo -dimensional transforms combined with frame to frame motion -adaptivity achieve highcompression ratios because they exploit pixel correlation in all three dimensions.

A steganographic technique inspired by rook is presented in this paper to ensure privacy and secrecy. In this approach, the cover image is partitioned into n × 1 pixel blocks and converted equivalent n × 8 binary bit planes. Then the functional output of each block is calculated on the basis of the number of rook positions, which are attacked by opponent rooks. The rook is a chess piece that moves only forward and backward in a straight line. In binary bit plane, 0 and 1 are considered as a black and white opponent rook, respectively. The secret information is considered as stream of binary bits. The binary bits of secret information are compared with the functional output of the corresponding block. If it is equal to the functional output of the corresponding block, then nothing needs to be done. In case of inequality, the small number of bits needs to be flipped in such a way that the functional output of the corresponding block becomes equal to the corresponding secret binary bits and the distortion of the cover is minimized.

The defining characteristic of a networked control system (NCS) is having a feedback loop that passes through a local area computer network. This paper considers nonlinear systems controlled in this manner, and demonstrates that for sufficiently high transmission rates, the network may be considered transparent. Three methods of scheduling data packets are compared: a static scheduler (token ring), the try-once-discard (maximum-error-first) scheduler with continuous priority levels, and the try-once-discard scheduler with discrete priority levels. The third method is of particular interest when only a small number of bits are available for collision resolution. Asymptotic stability is guaranteed in the first two cases, and ultimate uniform boundedness in the third. In the final section, simulations demonstrate the theoretical results. The contributions of this paper are two-fold: first, it extends the earlier results on NCS to nonlinear systems, and second, it allows for finite word-length message identifiers.

This paper introduces a best approach for Least Significant Bit (LSB) based on image steganography that enhances the existing LSB substitution techniques to improve the security level of hidden information. It is a new approach to substitute LSB of RGB true color image. The new security conception hides secret information within the LSB of image where a secret key encrypts the hidden information to protect it from unauthorized users. In general, in LSB methods, hidden information is stored into a specific position of LSB of image. For this reason, knowing the retrieval methods, anyone can extract the hidden information. In our paper, hidden information is stored into different position of LSB of image depending on the secret key. As a result, it is difficult to extract the hidden information knowing the retrieval methods. We have used the Peak Signal-to-Noise Ratio (PSNR) to measure the quality of the stego images. The value of PSNR gives better result because our proposed method changes very small number of bits of the image. The obtained results show that the proposed method results in LSB based image steganography using secret key which provides good security issue and PSNR value than general LSB based image steganography methods.