CLICHE network on chip: A novel multichannel acquisition module for a high throughput architecture

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss.

We analyze a new wormhole routing scheme, which we call the wormhole deflection with virtual channels (abbreviated WDVC) scheme, that combines wormhole routing with virtual channels and deflection routing to provide efficient lossless communication. We use new analytical models to analyze the performance of the WDVC scheme for the Manhattan Street (MS) network topology. In particular, we examine the effect of the traffic load and the number of virtual channels on the throughput and the length of paths followed by the worms, and compare the analytical results obtained with corresponding simulation results. Our results indicate that wormhole deflections combined with virtual channels is efficient under both light and heavy traffic loads, especially when the number of virtual channels on a link is large.

The adaptive routing approach has been expected as a promising way to improve network performance by utilizing available network bandwidth. Previous adaptive routing strategies in wormhole-routed multicomputer networks restrict the routing of messages by the routing algorithm to prevent deadlock. This results in low degree of adaptivity and low utilization of physical or virtual channels. In this paper, we examine the possibility of performing restriction-free adaptive routing in wormhole-routed networks as an approach to further improving the performance of these networks. A new flow control policy, called message cutting-in, is proposed, and two adaptive routing strategies are presented. Freedom of communication deadlock is achieved by the proposed flow control policy. The proposed adaptive routing strategies do not restrict routing and maximally utilize the physical and virtual channels. Simulation results show that the restriction-free adaptive routing approach is promising from the fact that it has the lowest latency and highest throughput depending on the number of virtual channels per physical channel and patterns of message traffic.

A new deadlock prevention scheme for nonminimal adaptive wormhole routing

Wormhole routing makes the communication latency insensitive of the network diameter and reduces the buffer size of each router. It has been widely adopted in many new generation distributed memory multiprocessor systems (DMMPs). The concept of virtual system is invented for deadlock-free routing design. Using a great deal of virtual channels is quite expensive to be implemented in practice and is not limitless. In this paper experimental results are given to evaluate the tradeoff between network congestion delay and throughput. Some results show that the congestion delay does not reduce visibly when the number of virtual channels is greater than that of internal channels by 2. A reasonable number of virtual channels can be derived from the results. A virtual networks system using only four virtual networks, two virtual channels in each direction, is presented. It shows that the minimum number of virtual networks to support a partially adaptive, minimal and deadlock free routing in k-ary n-cubes is just four. It uses only four virtual networks but can get a high degree of adaptiveness and high traffic capacity. Simulation results are presented to verify the performance.

The Voxel Imaging PET (VIP) Pathfinder project intends to show the advantages of using pixelated solid-state technology for nuclear medicine applications. It proposes designs for Positron Emission Tomography (PET), Positron Emission Mammography (PEM) and Compton gamma camera detectors with a large number of signal channels (of the order of 106). For Compton camera, especially with a large number of readout channels, image reconstruction presents a big challenge. In this work, results are presented for the List-Mode Ordered Subset Expectation Maximization (LM-OSEM) image reconstruction algorithm on simulated data with the VIP Compton camera design. For the simulation, all realistic contributions to the spatial resolution are taken into account, including the Doppler broadening effect. The results show that even with a straightforward implementation of LM-OSEM, good images can be obtained for the proposed Compton camera design. Results are shown for various phantoms, including extended sources and with a distance between the field of view and the first detector plane equal to 100 mm which corresponds to a realistic nuclear medicine environment.

Network-on-Chip (NoC) links consume a significant fraction of the total NoC power. We present Selective Packet Interleaving (SPI), a flit transmission scheme that reduces power consumption in NoC links. SPI decreases the number of bit transitions in the links by exploiting the multiplicity of virtual channels in a NoC router. SPI multiplexes flits to the router's output link so as to minimize the number of bit transitions from the previously transmitted flit. Analysis and simulations demonstrate a reduction of up to 55% in the number of bit transitions and up to 40% savings in power consumed on the link. SPI benefits grow with the number of virtual channels. SPI works better for links with a small number of bits in parallel. While SPI compares favorably against bus inversion, combining both schemes helps to further reduce bit transitions.

Carrier-sense multiple access (CSMA) algorithms have recently received significant interests in the literature for designing wireless control algorithms. CSMA algorithms incur low complexity and can achieve the optimal capacity under certain assumptions. However, CSMA algorithms suffer the starvation problem and incur large delay that may grow exponentially with the network size. In this paper, our goal is to develop a new algorithm that can provably achieve high throughput utility and low delay with low complexity. Toward this end, we propose a new CSMA-like algorithm, called Virtual-Multi-Channel CSMA (VMC-CSMA), that can dramatically reduce delay. The key idea of VMC-CSMA to avoid the starvation problem is to use multiple virtual channels (which emulate a multichannel system) and compute a good set of feasible schedules simultaneously (without constantly switching/recomputing schedules). Under the protocol interference model and a single-hop utility-maximization setting, VMC-CSMA can approach arbitrarily close-to-optimal system utility with both the number of virtual channels and the computation complexity increasing logarithmically with the network size. Furthermore, once VMC-CSMA converges to the steady state, we can show that under certain assumptions on the utility functions and the topology, both the expected packet delay and the tail distribution of the head-of-line (HOL) waiting time at each link can be bounded independently of the network size. Our simulation results confirm that VMC-CSMA algorithms indeed achieve both high throughput utility and low delay with low-complexity operations.

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

Current High-Performance Computing (HPC) and data center networks rely on large-radix routers. Hamming graphs (Cartesian products of complete graphs) and dragonflies (two-level direct networks with nodes organized in groups) are some direct topologies proposed for such networks. The original definition of the dragonfly topology is very loose, with several degrees of freedom, such as the inter- and intragroup topology, the specific global connectivity, and the number of parallel links between groups (or trunking level). This work provides a comprehensive analysis of the topological properties of the dragonfly network, providing balancing conditions for network dimensioning, as well as introducing and classifying several alternatives for the global connectivity and trunking level. From a topological study of the network, it is noted that a Hamming graph can be seen as a canonical dragonfly topology with a high level of trunking. Based on this observation and by carefully selecting the global connectivity, the Dimension Order Routing (DOR) mechanism safely used in Hamming graphs is adapted to dragonfly networks with trunking. The resulting routing algorithms approximate the performance of minimal, nonminimal, and adaptive routings typically used in dragonflies but without requiring virtual channels to avoid packet deadlock, thus allowing for lower cost router implementations. This is obtained by properly selecting the link to route between groups based on a graph coloring of network routers. Evaluations show that the proposed mechanisms are competitive with traditional solutions when using the same number of virtual channels and enable for simpler implementations with lower cost. Finally, multilevel dragonflies are discussed, considering how the proposed mechanisms could be adapted to them.

Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.

Recently, the growth of applications and services over high-speed Internet increases, ATM networks as wide area back-bone has been a major solution. As the conventional TCP/IP suite is still the standard protocol used to support upper application on current. Internet, the issues regarding whether TCP/IP will operate efficiently on top of an ATM infrastructure and how to control its QoS still remain for studies. TCP uses a window-based protocol for flow control in the transport layer. When TCP uses the UBR service in ATM layer, the control method is only buffer management. If a cell is discarded in ATM layer, one whole packet of TCP will be lost; this fact occur the most TCP performance degradation. Several dropping strategies, such as Tail Drop, EPD, PPD, SPD, FBA, have been proposed to improve the TCP performance over ATM. In this paper, to improve the TCP performance, we propose a packet dropping scheme that is based on comparison with EPD, SPD and FBA. Our proposed scheme is applied to schemes discussed in the previous technology. Our proposed scheme does not need to know each connection's mean packet size. When the buffer exceeds the given threshold, it is based on comparison between the number of dropped packet and the approved packet. Our results are reported and discussed for comparing these discarding schemes under similar conditions. Although the number of virtual channel (VC) is increased, the simulation results showed that the proposed scheme can allocate more fairly each VC than other scheme.

An experimental study was conducted using a network simulator to investigate the performance of packet communication networks as a function of: the network resource capacities (channels, buffers), the network load (number of virtual channels, virtual channel loads), protocols (flow control, congestion control, routing), and protocol parameters (virtual channel window size, input buffer limits). Performance characteristics are shown and the design of input buffer limits for network congestion control, virtual channel window size, and nodal buffer capacity addressed. Network design strategies for the control of load fluctuations are proposed and discussed.

Networks-on-Chip (NoCs) for embedded multiprocessor architectures require special mechanisms for sharing resources such as links and queues in network routers. A widely used solution is virtual-channel flow control which prevents head-of-line blocking and isolates different data streams. However, the number of virtual channels (VCs) is limited by the available buffer space in the routers. Due to the evergrowing number of applications and mutual exclusive requirements it may not be possible to assign each application a unique VC. In this paper we present a Resource Broker (RB) which is an overarching mechanism that schedules NoC traffic. It allows predictable and efficient sharing of VCs without compromising isolation and Quality-of-Service guarantees. We show that by managing the NoC traffic with the RB, we drastically reduce blocking and improve the overall utilization and hence the system performance.

Deadlock recovery as a viable alternative to deadlock avoidance has recently gained an increasing consideration in the scientific community. In this paper we present a simple and efficient minimal adaptive wormhole routing algorithm that recovers from potential deadlocks. Rather than using a static or dynamic channel dependency graph, we remove from the network those packets that have stalled for more than a given timeout in a router. The experimental results, conducted on a 256 nodes bi-dimensional tones show that it is possible to find a timeout which is optimal for several communication patterns. Our algorithm provides good network latency, stable throughput above saturation and compares well with a deterministic and a minimal adaptive algorithm based on Duato's methodology with the same number of virtual channels.