An Experimental Study of Building Blocks of Lattice-Based NIST Post-Quantum Cryptographic Algorithms

This research evaluated the practicality of implementing Post-Quantum Cryptography (PQC) algorithms onboard resource-constrained computing devices. While PQC is computationally efficient, key sizes, memory usage, and bandwidth constraints are of concern in an embedded environment. The Controller Area Network (CAN) protocol serves as an example of limited communication in an arbitrary embedded environment. It utilizes only eight (8) bytes of data payload per message, requiring the large keys of PQC algorithms to be split into several messages. Improvements upon the CAN protocol exist to increase throughput, although the unmodified version remains in use. This research is likely to be more restricted than future development. Comparison was made between PQC and current standard algorithms to evaluate computational cost. Ultimately, this research determined that PQC algorithms such as CRYSTALS-Kyber [1], CRYSTALS-Dilithium [2], and Falcon [3] are presently viable in low capacity networks.

Introduction. Widespread use of unmanned aerial vehicles in the civilian and military spheres requires the development of new algorithms for identification friend or foe of targets, as used in the Armed Forces of Ukraine (AFU) devices of the "Parol" system are designed to service approximately 110 objects military equipment. AFU automation systems allow the use of additional sources of information about various objects from civil or special data transmission networks, which can be the basis for building a networked multi-level system of state recognition. Predictions of the development of quantum computers foresee the possibility of breaking modern algorithms for information security in polynomial time in the next 5-10 years, which requires the development and implementation of new encryption algorithms and revision of modern parameters. The purpose of the article is to develop a new algorithm for state recognition of objects, which can be scaled to process the required number of manned and unmanned aerial vehicles. Potential threats to classical cryptographic protection algorithms for data networks, which will result in the execution of algorithms such as Grover and Shore on quantum computers, were also discussed. Results. The article proposes a new multilevel algorithm of state recognition based on modern cryptographic methods of information protection, which allows to perform reliable automated identification of objects, scale systems using data on potential targets from other sources through secure special networks. Grover's search algorithm does not give a strong increase in key search performance for symmetric encryption algorithms, so there is no need to increase the key lengths for this type of information security algorithms. Post-quantum asymmetric encryption algorithms require additional study and comprehensive testing of information security or increasing the key lengths of cryptographic algorithms, which corresponds to the number of qubits, i.e. more than twice. The most promising is the family of asymmetric post-quantum cryptographic algorithms based on supersingular isogenic elliptic curves. Conclusions. The developed algorithm of identification friend or foe of objects is more secure compared to existing algorithms and is focused on the use of modern on-board computers and programmable radio modems. Shore's algorithm and the like will be a significant threat to modern asymmetric cryptography algorithms when the number of qubits of quantum computers exceeds the number of bits in public keys more than twice. Keywords: identification friend or foe, symmetric encryption, asymmetric cryptography, quantum computer, post-quantum cryptography.

The increasing complexity of instrumentation in science and industry has lead to a growth in the use of Application Specific Integrated Circuits (ASICs). Solutions using ASICs are very cost efficient in high volume production. They are also very valuable when instrument volume, functionality, and reliability are the main issues. In the standard cell approach, the ASIC designer is allowed to use predefined functional building blocks as an aid in the design process. This is advantageous when using a high-level design methodology for the digital circuits. Preverified models exist for the analogue and the digital standard cells, and thus the standard cell approach is very similar to using Field Programmable Gate Arrays (FPGAs). However, using standard cells, as opposed to full custom design techniques, leads to degraded flexibility and performance in terms of circuit density and speed. On the other hand one gains design time.

Cryptographic algorithms are crucial for secure communication in the Internet of Things (IoT). Quantum computers threaten public key cryptography algorithms like RSA (Rivest, Shamir, Adleman) and Diffie-Hellman (DH) key exchange schemes, which are widely in use today. As cryptographic algorithms are the foundation of secure internet communication, the development of Quantum Key Distribution (QKD) and Post-Quantum Cryptography (PQC) is essential to protect transactions over the internet. However, solutions like Quantum Key Distribution require heavy infrastructure. So, it is not feasible for the Internet of Things with fewer resources in computing power and form factor. Post-Quantum Cryptography is helpful on these devices. But, it needs further developments and improvements. This paper analyzes cryptography algorithms and protocols of IoT with different categories. Integrated PQC of National Institute of Standards and Technology (NIST) third level finalists on Raspberry Pi 4 (RPI4) board with Linux operating system. The performance of Post-Quantum Cryptography schemes for IoT has been evaluated. Finally, a Post-Quantum Cryptography scheme has been suggested for the Internet of Things based on the performance analysis.

Due to high functional variety, wide power rating range, and relatively low product volumes, electronic systems for industrial application are difficult to economically be integrated on a chip. This paper presents the smart power gate array (SPGA), a novel application-specific integrated circuit (ASIC) platform exactly aimed at enabling cost-efficient single-chip integration of industrial electronic systems. The SPGA combines a low-voltage mixed-signal gate array with a structured high-voltage smart-power core, allowing for single-chip integration of signal conditioning, data processing, power management, actuator driving, and line communication functionalities required for industrial applications. Simultaneously, it offers low nonrecurring engineering cost and high design flexibility owning to the utilized gate array technology. In this paper, the SPGA concept is introduced to overcome integration limitations of existing ASIC technologies. Then, design and capabilities of the SPGA functional modules are described. Finally, a practical SPGA application example of single-chip integrated solenoid valve control and monitoring system is demonstrated.

Post-quantum cryptography is considered to provide security against both traditional and quantum computer attacks. Dilithium is a digital signature algorithm that derives its security from the challenge of finding short vectors in lattices. It has been selected as one of the standardizations in the NIST post-quantum cryptography project. Hardware-software co-design is a commonly adopted implementation strategy to address various implementation challenges, including limited resources, high performance, and flexibility requirements. In this study, we investigate using compact instruction set extensions (ISEs) for Dilithium, aiming to improve software efficiency with low hardware overheads. To begin with, we propose tightly coupled accelerators that are deeply integrated into the RISC-V processor. These accelerators target the most computationally demanding components in resource-constrained processors, such as polynomial generation, Number Theoretic Transform (NTT), and modular arithmetic. Next, we design a set of custom instructions that seamlessly integrate with the RISC-V base instruction formats, completing the accelerators in a compact manner. Subsequently, we implement our ISEs in a chip design for the Hummingbird E203 core and conduct performance benchmarks for Dilithium utilizing these ISEs. Additionally, we evaluate the resource consumption of the ISEs on FPGA and ASIC technologies. Compared to the reference software implementation on the RISC-V core, our co-design demonstrates a remarkable speedup factor ranging from 6.95 to 9.96. This significant improvement in performance is achieved by incorporating additional hardware resources, specifically, a 35% increase in LUTs, a 14% increase in FFs, 7 additional DSPs, and no additional RAM. Furthermore, compared to the state-of-the-art approach, our work achieves faster speed performance with a reduced circuit cost. Specifically, the usage of additional LUTs, FFs, and RAMs is reduced by 47.53%, 50.43%, and 100%, respectively. On ASIC technology, our approach demonstrates 12, 412 cell counts. Our co-design provides a better tradeoff implementation on speed performance and circuit overheads.

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

Post-quantum cryptography is an emerging solution to the expected security breach, introduced by quantum computers, to the currently used public key cryptosystems. This paper presents an experimental study on the effect of the overhead associated with the wireless transmission of some of the newly developed post quantum cryptography algorithms through the Internet of Things networks. Experimental results of this work include the energy and time measurements for wireless transmission of chosen sample messages of these new cryptographic algorithms. In addition, recommendations are given for appropriate modules configurations and choice of suitable security algorithm for the Internet of Things networks.

In this paper, we describe a new low-leakage standard cell based application-specific integrated circuit (ASIC) design methodology. This design is based on the use of modified standard cells, designed to reduce leakage currents (by almost two orders of magnitude) in standby mode and also allow precise estimation of leakage current. For each cell in a standard cell library, two low-leakage variants of the cell are designed. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and similarly we minimize leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants of each standard cell are obtained. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design. We have performed experiments to compare placed-and-routed area, leakage and delays of this new methodology against Multithreshold CMOS (MTCMOS) and a regular standard cell based design style. The results show that our new methodology (which we call the "HL" methodology) has better speed and area characteristics than MTCMOS implementations. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude lower than the leakage of traditional standard cells. An ASIC design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement. Another advantage of our methodology is that the leakage is precisely estimable, in contrast with MTCMOS. Our primary contribution in this paper is a new low leakage design style for static CMOS designs. In addition, we also discuss techniques to reduce leakage in dynamic (domino logic) designs

Convolution neural networks (CNNs) as one of today's main flavor of deep learning techniques dominate in various image recognition tasks. As the model size of modern CNNs continues to grow, neural network compression techniques have been proposed to prune the redundant neurons and synapses. However, prior techniques disconnect the software neural networks compression and hardware acceleration, which fail to balance multiple design parameters, including sparsity, performance, hardware area cost, and efficiency. More concretely, prior unstructured pruning techniques achieve high sparsity at the expense of extra performance overhead, while prior structured pruning techniques relying on strict sparse patterns lead to low sparsity and extra hardware cost. In this article, we propose OMNI, a framework for accelerating sparse CNNs on hardware accelerators. The innovation of OMNI stems from that it uses hardware amenable on-chip memory partition patterns to seamlessly engage the software CNN model compression and hardware CNN acceleration. To accelerate the compute-intensive convolution kernel, a promising hardware optimization approach is memory partition, which divides the original weight kernels into several groups so that the different hardware processing elements can simultaneously access the weight. We exploit the memory partition patterns including block, cyclic, or hybrid as a means of CNN compression patterns. Our software CNN model compression balances the sparsity across different groups and our hardware accelerator employs hardware parallelization coordinately with the sparse patterns, leading to a desirable compromise between sparsity and performance. We further develop performance models to help the designers to quickly identify the pattern factors subject to an area constraint. Last, we evaluate our design on application specific integrated circuit (ASIC) and field-programmable gate array (FPGA) platform. Experiments demonstrate that OMNI achieves 3.4×- 6.2× speedup for the modern CNNs, over a comparably ideal dense CNN accelerator. OMNI shows 114.7× energy efficiency improvement compared with GPU platform. OMNI is also evaluated on Xilinx ZC706 and ZCU102 FPGA platforms, achieving 41.5 GOP/s and 125.3 GOP/s, respectively.

Delay generator (DG) generating a digitally programmed time interval acts as the core component in various modern physical experiments. Most traditional designs are based on application specific integrated circuit (ASIC) platform causing long development period and high cost. This work presents a high-resolution Vernier DG architecture based on field programmable gate array (FPGA) platform, which utilizes a novel delay line structure built on multiplexed carry chain. The carry chain structure guarantees the resolution rather small. The multiplexer laid next to the carry chain makes the actual delay of the delay line dynamically adjustable. This structure can be automatically compiled by PC without manual intervene while maintaining very high resolution. A DG prototype circuit was implemented on a Stratix III FPGA and experimental tests were conducted to evaluate the performance. The obtained resolution is 23.9 ps, the differential nonlinearity (DNL) lies in the range of -0.62 least significant bit (LSB) ~ 0.59 LSB and the integral nonlinearity (INL) lies in the range of -0.14 LSB ~ 0.01 LSB. All the performances show state-of-the-art quality.

Chapter 17 - Application-Specific Integrated Circuits (ASICs)

In this work an NTT-based (Number Theoretic Transform) multiplier for code-based Post-Quantum Cryptography (PQC) is presented, supporting Quasi Cyclic Low/Moderate-Density Parity-Check (QC LDPC/MDPC) codes. The cyclic matrix product, which is the fundamental operation required in this application, is treated as a polynomial product and adapted to the specific case of QC-MDPC codes proposed for Round 3 and 4 in the National Institute of Standards and Technology (NIST) competition for PQC. The multiplier is a fundamental component in both encryption and decryption, and the proposed solution leads to a flexible NTT-based multiplier, which can efficiently handle all types of required products, where the vectors have a length &#x2248;104 and can be moderately sparse. The proposed architecture is implemented using both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) technologies and, when compared with the best published results, it features a 10 times reduction of the encryption times with the area increased by 3 times. The proposed multiplier, incorporated in the encryption and decryption stages of a code-based PQC cryptosystem, leads to an improvement over the best published results between 3 to 10 times in terms of <inline-formula> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> product (LUT times latency).

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{a}$ </tex-math></inline-formula>, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

The staggering innovations and emergence of numerous deep learning (DL) applications have forced researchers to reconsider hardware architecture to accommodate fast and efficient application-specific computations. Applications, such as object detection, image recognition, speech translation, as well as music synthesis and image generation, can be performed with high accuracy at the expense of substantial computational resources using DL. Furthermore, the desire to adopt Industry 4.0 and smart technologies within the Internet of Things infrastructure has initiated several studies to enable on-chip DL capabilities for resource-constrained devices. Specialized DL processors reduce dependence on cloud servers, improve privacy, lessen latency, and mitigate bandwidth congestion. As we reach the limits of shrinking transistors, researchers are exploring various application-specific hardware architectures to meet the performance and efficiency requirements for DL tasks. Over the past few years, several software optimizations and hardware innovations have been proposed to efficiently perform these computations. In this article, we review several DL accelerators, as well as technologies with emerging devices, to highlight their architectural features in application-specific integrated circuit (IC) and field-programmable gate array (FPGA) platforms. Finally, the design considerations for DL hardware in portable applications have been discussed, along with some deductions about the future trends and potential research directions to innovate DL accelerator architectures further. By compiling this review, we expect to help aspiring researchers widen their knowledge in custom hardware architectures for DL.