An implementation of multiple‐valued logic circuit with cmos multiple‐valued output gates

This paper proposes a new construction of bipolar current‐mode (CML) logic circuits based on the multiple‐valued logic concept. Applying the multiple‐valued logic concept, the new logic function, which can replace the conventional stack logic circuit and can be operated by a low supply voltage, can be realized. In conventional circuits, it is difficult to generate a signal with multiple voltage levels at the same time as the output of a logic gate and logic gates must be connected by placing a level‐shifter between them.A circuit is devised in this study that generates the multiple‐valued logic levels (three levels in this paper) simultaneously at the output of the logic gate. Also, it is examined whether or not the basic logic functions, such as NAND, NOR, EX‐OR, and D‐Latch, can be realized by the proposed configuration. The characteristics of the proposed circuit are circuit simulated by a SPICE circuit simulator. It is seen as a result that the power consumption, the logic density, and the high‐speed performances, comparable to the conventional stacked‐gate logic circuit, can be realized with the low supply voltage of 1.9 V.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

In the universal literal circuit (ULC) previously proposed, since the two threshold values of the literal circuit are variable by external control signals, four‐valued logic circuits have attracted considerable attention. However, to realize LSI, there was room for improvement from the viewpoint of power consumption.In this paper, as a literal, with the other characteristics remaining the same, a new low‐power ULC circuit with power consumption decreased by 1/285 is proposed. Also, the threshold voltage variation due to the body‐effect of MOS transistors, having a critical influence on the level discrimination characteristics of the circuit, is solved by introducing body‐effect compensating transistors. Moreover, by SPICE simulation, it is verified that the low‐power ULC works satisfactorily.

In the design of logic circuits, it is not always true that the circuit constructed by the designer is the optimal one. From such a viewpoint, this paper proposes a method in which the first designed circuit is expanded backwardly, i.e., from the output back to the input, and more than one equivalent circuit of the same function is resynthesized and the one best satisfying the requirements is determined and adopted.In the proposed method, a fuzzy reasoning is introduced in the decision process. In this scheme, such requirements as the delay time, power consumption and the chip area are handled by the fuzzy reasoning. A selectability index known as “selection criterion value” is given to each generated circuit, and the objective logic circuit is selected according to this index.Such requirements as delay, etc., have different units and are often in a trade‐off relation. Therefore, these requirements are represented as relative values and are considered as circuit selection parameters in the fuzzy reasoning. Such parameterization enables easy understanding of the features of each circuit. It is easy also to decide which of the parameters of the trade‐off relation is to be emphasized in the selection process.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.

After using side-channel information leaked by the FPGA chip which is embedded with a block cipher algorithm, there is a scheme called improved combinational side-channel attack. This scheme mainly aimed at logical circuits implemented in S-box in background of power consumption attack and we make a level of models by power consumption in combinational logic circuits which is engendered by glitches different from traditional sequential logical circuits which is engendered by flip in the output of register with the Hamming model. In addition, we take advantage of match algorithm in a linear model and in multivariate Gaussian model from template attack to process an important data twice and the key would be recovered. At last, we make a comparison between Hamming model and our model. And prove that this paper improved the attacking efficiency and accuracy and also provided a clue to the security cipher chip from countermeasures.

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

This study presents new low‐power multiple‐valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)‐based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P‐ and N‐type devices. These characteristics make CNTFETs very suitable for designing high‐performance multiple‐ V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET‐based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm‐CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state‐of‐the‐art ternary and quaternary circuits.

The capture of phosphoproteins by 14-3-3 proteins mediates actions of insulin

Over the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this paper, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits.

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

In recent years the evolution of digital circuits has been intensively studied. This paper proposes an elitist pool evolutionary algorithm based on novel approach in order to improve evolutionary design of logic circuits in efficiency and capability of optimization. In the process of evolution, a novel sub-circuit crossover strategy can improve the local optimization by inheriting the better parts of two parental circuits, and an adaptive mutation strategy based on importance of gene-position can maintain the diversity of a population. Experiments show that the proposed method is able to design logic circuits efficiently.

Since the scalability of logic circuits is becoming larger and more complex, the auto-design is becoming more and more difficult. In order to improve automatic design and performance evaluation of logic circuits in efficiency and capability of optimization, multiobjective simulated annealing (MSA) based increasable evolution approach is designed to evolve logic circuits automatically with an extended matrix encoding method, which can be able to reflect the potential performance of a circuit and reduce the risk of deleting a circuit with a good developing potential during evolution is devised. In the process of evolution, each individual is renewedly associated to a corresponding objective in terms of a novel adaptive evaluation method at each generation. In experiments, complicated arithmetic circuits are designed to assess the performance of MSA against other algorithms. Results indicate that the proposed method could design logic circuits efficiently.

본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 <TEX>$16\;{\times}\;16$</TEX> 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류 모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 <TEX>$0.18\;{\mu}m$</TEX> CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다. This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The <TEX>$16{\times}16$</TEX> bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung <TEX>$0.18\;{\mu}m$</TEX> standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.