An Improved Adaptive Digital Predistortion Using Discrete Newton's Method

In this paper, a method for improving feedback signal distortion over-compensation of a digital pre-distortion(DPD) system is presented. The method comprises the following steps: acquiring a distortion compensation characteristic parameter of an input signal in a forward channel of the digital pre-distortion system to form a forward channel distortion compensation lookup table(LUT), and compensating the input signal before digit-analog converter (DAC); acquiring an ideal compensation characteristic parameter of the input signal in a small closed loop without power amplification to form a feedback signal distortion compensation LUT for compensating in a feedback signal; and acquiring an ideal compensation characteristic parameter of the input signal in a big closed loop with power amplification to form a digital pre-distortion LUT dealing with power amplification non-linear distortion for compensating in the forward signal. Through the method, the over-compensation characteristic of the feedback signal can be further effectively counter balanced based on compensation to forward channel distortion to achieve the aim of improving the performance of the digital pre-distortion system.

Sparse newton-like methods in equation oriented flowsheeting

Preface 1. Introduction. Problems to be considered Characteristics of 'real-world' problems Finite-precision arithmetic and measurement of error Exercises 2. Nonlinear Problems in One Variable. What is not possible Newton's method for solving one equation in one unknown Convergence of sequences of real numbers Convergence of Newton's method Globally convergent methods for solving one equation in one uknown Methods when derivatives are unavailable Minimization of a function of one variable Exercises 3. Numerical Linear Algebra Background. Vector and matrix norms and orthogonality Solving systems of linear equations-matrix factorizations Errors in solving linear systems Updating matrix factorizations Eigenvalues and positive definiteness Linear least squares Exercises 4. Multivariable Calculus Background Derivatives and multivariable models Multivariable finite-difference derivatives Necessary and sufficient conditions for unconstrained minimization Exercises 5. Newton's Method for Nonlinear Equations and Unconstrained Minimization. Newton's method for systems of nonlinear equations Local convergence of Newton's method The Kantorovich and contractive mapping theorems Finite-difference derivative methods for systems of nonlinear equations Newton's method for unconstrained minimization Finite difference derivative methods for unconstrained minimization Exercises 6. Globally Convergent Modifications of Newton's Method. The quasi-Newton framework Descent directions Line searches The model-trust region approach Global methods for systems of nonlinear equations Exercises 7. Stopping, Scaling, and Testing. Scaling Stopping criteria Testing Exercises 8. Secant Methods for Systems of Nonlinear Equations. Broyden's method Local convergence analysis of Broyden's method Implementation of quasi-Newton algorithms using Broyden's update Other secant updates for nonlinear equations Exercises 9. Secant Methods for Unconstrained Minimization. The symmetric secant update of Powell Symmetric positive definite secant updates Local convergence of positive definite secant methods Implementation of quasi-Newton algorithms using the positive definite secant update Another convergence result for the positive definite secant method Other secant updates for unconstrained minimization Exercises 10. Nonlinear Least Squares. The nonlinear least-squares problem Gauss-Newton-type methods Full Newton-type methods Other considerations in solving nonlinear least-squares problems Exercises 11. Methods for Problems with Special Structure. The sparse finite-difference Newton method Sparse secant methods Deriving least-change secant updates Analyzing least-change secant methods Exercises Appendix A. A Modular System of Algorithms for Unconstrained Minimization and Nonlinear Equations (by Robert Schnabel) Appendix B. Test Problems (by Robert Schnabel) References Author Index Subject Index.

Chapter 65 - Computer art from Newton's, Ssecant, and Richardson's methods

This paper presents adaptive phase-only memory digital pre-distortion (DPD) and gain/phase/delay imbalance correction techniques for outphasing power amplifiers (PAs). Least squares adaptation is used for the phase-only DPD and imbalance correction techniques. The performance of these techniques is verified by co-simulations and measurements of an outphasing PA implemented with two identical class-F PAs and a Chireix combiner. The Chireix combiner with compensating stubs added to achieve high efficiency introduces nonlinearity. The proposed adaptive phase-only memory DPD corrects for the nonlinearity due to the Chireix combiner. The proposed gain/phase/delay imbalance correction technique achieves total lower/upper adjacent channel power ratio (ACPR) improvements of 43.8/37.6 dB for 5-MHz and 46.2/38.3 dB for 10-MHz long-term-evolution signals in measurements. The fractional-sample delay imbalance correction reduces distortion at low input amplitudes and demonstrates on the order of a 10-dB ACPR improvement compared to full-sample delay imbalance correction.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

An algebraic description of basic discrete symmetries (space reversal P, time reversal T, and their combination PT) is studied. Discrete subgroups of orthogonal groups of multidimensional spaces over the fields of real and complex numbers are considered in terms of fundamental automorphisms of Clifford algebras. In accordance with a division ring structure, a complete classification of automorphism groups is established for the Clifford algebras over the field of real numbers. The correspondence between eight double coverings (Dąbrowski groups) of the orthogonal group and eight types of the real Clifford algebras is defined with the use of isomorphisms between the automorphism groups and finite groups. Over the field of complex numbers there is a correspondence between two nonisomorphic double coverings of the complex orthogonal group and two types of complex Clifford algebras. It is shown that these correspondences associate with a well-known Atiyah–Bott–Shapiro periodicity. Generalized Brauer–Wall groups are introduced on the extended sets of the Clifford algebras. The structure of the inequality between the two Clifford–Lipschitz groups with mutually opposite signatures is elucidated. The physically important case of the two different double coverings of the Lorentz groups is considered in details.

This paper presents an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whose implementation and real time adaptation have been fully performed in a Field Programmable Gate Array (FPGA) device responsible for the co-processing tasks. The predistortion function is carried out in a Basic Predistortion Cell (BPC) containing a Look-up Table (LUT). One of the main advantages of this DPD configuration is that adaptation is performed in a hot manner and therefore, it is not necessary to switch the DPD into a training mode in order to estimate the LUT contents. Results showing the linearization capabilities of this adaptive DPD are here provided.

A digital pre-distortion (DPD) scheme based on an adaptive-memory-length look-up table (AML-LUT) is proposed and experimentally demonstrated in a four-level pulse amplitude modulation (4-PAM) underwater optical wireless communication (UOWC) system. By implementing adaptive memory length for each pattern in the AML-LUT-based DPD, the size of the AML-LUT can be significantly reduced without sacrificing performance compared to both the full-size LUT and the multi-symbol simplified look-up table (MSS-LUT)-based DPDs. The performance of the proposed AML-LUT-based DPD is experimentally evaluated for a 625 Mbit/s 4-PAM UOWC over 1 m transmission length. Experimental results show that compared with the full-size LUT with a memory length of 7 (LUT-7)-based DPD, the proposed AML-LUT-based DPD (i) incurs a marginal power penalty of 0.5 dB at both the 7% hard-decision forward error correction (HD-FEC) and KP4-FEC threshold limits, while simultaneously reducing the implementation complexity (i.e., the LUT size) by 93%; (ii) achieves comparable transmission performance compared to the MSS-LUT-based DPD, while reducing the implementation complexity by 89%; and (iii) shows great potential for high-speed, low-complexity and memory-efficient intensity modulation and direct detection (IM/DD) UOWC and short-reach optical interconnects.

Chapter 13 - Open Root Finding Methods

In this article, we study digital predistortion (DPD)-based linearization with a specific focus on millimeter-wave (mmW) active antenna arrays. Due to the very large-channel bandwidths and beam-dependence of nonlinear distortion in such systems, we present a closed-loop DPD learning architecture, lookup table (LUT)-based memory DPD models, and low-complexity sign-based estimation algorithms such that even continuous DPD learning could be technically feasible. To this end, three different learning algorithms-sign, signed regressor, and sign-sign-are formulated for the LUT-based DPD models such that the potential rank deficiencies, experienced in earlier methods, are avoided while facilitating greatly reduced learning complexity. The injection-based LUT DPD structure is also shown to allow for low numbers and reduced dynamic range of the involved LUT entries. Extensive RF measurements utilizing a state-of-the-art mmW active antenna array system at 28 GHz are carried out and reported to validate the methods, incorporating very wide channel bandwidths of 400 and 800 MHz while pushing the array close to saturation. In addition, the processing and learning complexities of the considered techniques are analyzed, which, together with the measured linearization performance figures, allows to assess the complexity-performance tradeoffs of the proposed solutions. Overall, the results show that efficient mmW array linearization can be obtained through the proposed methods at very low complexity.

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

This paper details the design of a Digital Predistorter (DPD) based on the Simplified Volterra Series (SVS) model. Our main contributions concern first the design of the predistorter unit using the Look Up Table (LUT) method without additional algorithms to decrease the high number of coefficients required for the PA model. Then, a Matlab and Modelsim cosimulation approach is discussed and performed to evaluate the proposed DPD architecture, in particular synthesis results are presented in terms of required Field Programmable Gate Array (FPGA) resources to implement the proposed predistorter. In addition, the performances of the proposed design are verified using a class AB GaN Power Amplifier (PA) driven by one carrier Long Term Evolution-Advanced (LTE-A) signal with 20 MHz channel bandwidth. It is proven that the LUT predistorter occupies only 55 % of the multipliers (DSP48E1) available in the Zynq-7000 FPGA. Also, the Adjacent Channel Power Ratio (ACPR) attains more than −45 dB.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

This paper deals with Field Programmable Gate Array (FPGA) implementation design of a Predistorter real-time processing. The corresponding Baseband Digital Predistortion (DPD) is based on Memory Polynomial (MP) modelling of a UHF 8 MHz LDMOS Power Amplifier (PA). The PA MP model coefficients are estimated based on Least Square Estimation (LSE) algorithm. The proposed DPD design is using Look Up Table (LUT) for the Predistorter unit and the Indirect Learning Architecture (ILA) approach for estimating the coefficients of the predistorter. Implementation test results for the UHF LDMOS PA with DVB-T modulated signals showed good linearization performances with the adjacent channel power ratio (ACPR) reaching −46 dB.