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  • https://doi.org/10.1007/978-3-642-25188-7_61Copy DOI Icon

An Improved Implementation Scheme for AVS Entropy Decoding Based on FPGA

  • Jan 1, 2011
  • Wen-Ge Zhu +2 more
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Abstract

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this paper. The additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing periods. And it makes the barrel shifter prepositive so as to balance the time sequence path in the front end. In this way, the deficiency in the traditional structure of variable length decoding is conquered. Compared with the traditional structure, the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition (4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

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