An Improved Page Replacement Algorithm Using Block Retrieval of Pages

Contemporary discrete GPUs support rich memory management features such as virtual memory and demand paging. These features simplify GPU programming by providing a virtual address space abstraction similar to CPUs and eliminating manual memory management, but they introduce high performance overheads during (1) address translation and (2) page faults. A GPU relies on high degrees of thread-level parallelism (TLP) to hide memory latency. Address translation can undermine TLP, as a single miss in the translation lookaside buffer (TLB) invokes an expensive serialized page table walk that often stalls multiple threads. Demand paging can also undermine TLP, as multiple threads often stall while they wait for an expensive data transfer over the system I/O (e.g., PCIe) bus when the GPU demands a page. In modern GPUs, we face a trade-o on how the page size used for memory management affects address translation and demand paging. The address translation overhead is lower when we employ a larger page size (e.g., 2MB large pages, compared with conventional 4KB base pages), which increases TLB coverage and thus reduces TLB misses. Conversely, the demand paging overhead is lower when we employ a smaller page size, which decreases the system I/O bus transfer latency. Support for multiple page sizes can help relax the page size trade-o so that address translation and demand paging optimizations work together synergistically. However, existing page coalescing (i.e., merging base pages into a large page) and splintering (i.e., splitting a large page into base pages) policies require costly base page migrations that undermine the benefits multiple page sizes provide. In this paper, we observe that GPGPU applications present an opportunity to support multiple page sizes without costly data migration, as the applications perform most of their memory allocation en masse (i.e., they allocate a large number of base pages at once). We show that this en masse allocation allows us to create intelligent memory allocation policies which ensure that base pages that are contiguous in virtual memory are allocated to contiguous physical memory pages. As a result, coalescing and splintering operations no longer need to migrate base pages. We introduce Mosaic, a GPU memory manager that provides application-transparent support for multiple page sizes. Mosaic uses base pages to transfer data over the system I/O bus, and allocates physical memory in a way that (1) preserves base page contiguity and (2) ensures that a large page frame contains pages from only a single memory protection domain. We take advantage of this allocation strategy to design a novel in-place page size selection mechanism that avoids data migration. This mechanism allows the TLB to use large pages, reducing address translation overhead. During data transfer, this mechanism enables the GPU to transfer only the base pages that are needed by the application over the system I/O bus, keeping demand paging overhead low. Our evaluations show that Mosaic reduces address translation overheads while efficiently achieving the benefits of demand paging, compared to a contemporary GPU that uses only a 4KB page size. Relative to a state-of-the-art GPU memory manager, Mosaic improves the performance of homogeneous and heterogeneous multi-application workloads by 55.5% and 29.7% on average, respectively, coming within 6.8% and 15.4% of the performance of an ideal TLB where all TLB requests are hits. CCS CONCEPTS • Computer systems organization → Parallel architectures;

Contemporary discrete GPUs support rich memory management features such as virtual memory and demand paging. These features simplify GPU programming by providing a virtual address space abstraction similar to CPUs and eliminating manual memory management, but they introduce high performance overheads during (1) address translation and (2) page faults. A GPU relies on high degrees of thread-level parallelism (TLP) to hide memory latency. Address translation can undermine TLP, as a single miss in the translation lookaside buffer (TLB) invokes an expensive serialized page table walk that often stalls multiple threads. Demand paging can also undermine TLP, as multiple threads often stall while they wait for an expensive data transfer over the system I/O (e.g., PCIe) bus when the GPU demands a page. In modern GPUs, we face a trade-off on how the page size used for memory management affects address translation and demand paging. The address translation overhead is lower when we employ a larger page size (e.g., 2MB large pages, compared with conventional 4KB base pages), which increases TLB coverage and thus reduces TLB misses. Conversely, the demand paging overhead is lower when we employ a smaller page size, which decreases the system I/O bus transfer latency. Support for multiple page sizes can help relax the page size trade-off so that address translation and demand paging optimizations work together synergistically. However, existing page coalescing (i.e., merging base pages into a large page) and splintering (i.e., splitting a large page into base pages) policies require costly base page migrations that undermine the benefits multiple page sizes provide. In this paper, we observe that GPGPU applications present an opportunity to support multiple page sizes without costly data migration, as the applications perform most of their memory allocation en masse (i.e., they allocate a large number of base pages at once).We show that this en masse allocation allows us to create intelligent memory allocation policies which ensure that base pages that are contiguous in virtual memory are allocated to contiguous physical memory pages. As a result, coalescing and splintering operations no longer need to migrate base pages.

Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an enVironment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.

The problem of determining page size in a page on demand system is discussed in detail in this paper. After having introduced the problem, the effect page size may have on various system performance measures is reviewed based on measurements of program behaviour and on simple models of system behaviour. This discussion is followed by a detailed study of the effect of the choice of page size on the efficient utilization of primary memory space. The wasted space-time integral (WSTI) of primary memory space is selected as a measure of this utilisation and a new model of program and system behaviour is used to compute the WSTI for different secondary memory devices (drum, ECS and LCS) and different system behaviour parameters such as the time spent in supervisor mode by the operating system to initiate a page transfer, the time spent in the CPU queue by a program which has recovered from a page fault before it receives the attention of the CPU, the global page fault rate (or arrival rate at the secondary storage devices used for paging) and other factors. The influence of each of these factors is discussed and analyzed, and the conditions under which one or another of these dominates the problem is identified. In the Appendix, one of the problems posed by our model, the use of approximate formulae for fragmentation which remain valid for a large class of probability distribution functions of program size, is analyzed in detail. Some tests are developed for the validity of these formulae.

We study characteristics of page fault behavior of programs under a demand paging system and propose two prepaging schemes: page premapping and page prefetching. Our studies on the page fault behavior show that a large number of page faults occur in the shared library or in the dynamic heap of programs and can be handled without disk access. For those page faults, we propose page premapping that tries to reduce page fault overhead by mapping the page(s) which will be referenced shortly in advance. Premapping is performed by page fault handler whenever a page fault occurs and can save many page faults needed otherwise to execute programs. When a process starts to run, the pages of the text and the initialized data segments must be read from disk at every page fault. In that case the process must wait for a faulted page while it is being read. So the page faults that occur at process start time exert a strong influence on its response time. For those page faults, we propose page prefetching that tries to reduce page-in delay by prefetching page(s) to be referenced shortly. Prefetching is effective in reducing the sleep times of processes due to disk access. Prefetching is performed asynchronously by a low priority kernel level process. Our prepaging schemes use hints that reflect the sequence of page references and the page fault behavior of the program. Experimental results show that our prepaging schemes induce little overhead and can improve the performance of several programs significantly.

How to Pack Trees

The Least Recently Used (LRU) policy is often used as a page replacement algorithm for virtual memory, and it is considered to be good. The major problem is that it is time consuming algorithm. This paper presents an efficient hardware FPGA implementation for LRU algorithm based on fuzzy logic with reduced inference rules. In this proposal, the page's recency of reference is used as input crisp variable to calculate the fuzzy value. Then a knowledge base that composed of five inference rules are used to calculate the page replacement weights for the pages in the memory. These pages' weights are used to select the victim page for replacement when there is a page fault and no empty page frame available in the memory. All stages starting from the crisp input values until the decision of selection the victim page to be replaced is implemented using very careful designed FPGA circuits. The main features of the design are focusing on the time speed of decision and the FPGA area. That is done in two ways, reducing the fuzzy rules to five only and using the best of the FPGA capability. The results show that the merging between fuzzy logic and FPGA implementation is very promising to achieve the LRU page replacement algorithm in real time.

Operating systems should support fine-grained objects in two important ways. One is the use of fairly small pages (e.g. 1 KB) and fast, flexible virtual memory primitives. Another is the use of a binary code format that supports precise identification of pointers in registers and stacks. These features can support many novel and efficient uses of conventional hardware. Pointer swizzling (address translation) at page fault time can efficiently support huge address spaces with modest word sizes. Compressed paging implements a new level in the memory hierarchy (compressed in-memory storage) to bridge the growing gap between RAM and disk. Adaptive prefetching promises to reduce page fault costs more effectively than increasing page sizes. Many other applications would also benefit, including garbage collection, checkpointing, distributed virtual memories, lazy evaluation, and memory striping to reduce cache conflicts. >

In this study we construct a simulator of a data base management system running in a virtual memory environment. We use the simulator to investigate the value of using an I/O buffer in this environment. The simulator is driven by trace data obtained with a software probe. The simulator is validated and is used to verify a theoretical model which predicts paging and disk access rates produced by use of an I/O buffer in a virtual memory environment. Results from a multi-factor set of simulation experiments are analyzed. The factors include three page replacement algorithms, four buffer management algorithms, five virtual buffer sizes, three values for real memory and six well known and widely differing distributions for creating sequences of requests to the simulated data base management system.

The article deals with José Gil’s considerations on the relationships between the virtuality and the actuality of the dancing body. At first, it analyses Gil’s idea of projecting the current position of the dancing body into virtual images and explores Gil’s notion of the multiplicity of virtuality. Further, it demonstrates how in the space of the body a consistent compound of movements is created at the level of the monstrous virtual body. Finally, the article emphasizes that, despite the connections between the actual position of the body and its virtual images, there is a fundamental distinction between the actuality and the virtuality of the dancing body. It shows that the idea of the distinction between the virtual and the actual reflects Gil’s concept of virtual memory as a zone of accumulated possibilities of movement.

Memory management systems are generally custom-made where the replacement algorithm deals only with the number of memory hits. So, to reduce the page fault rate, we are proposing a page replacement algorithm called Farthest Page Replacement (FPR) algorithm. More the page faults lesser the performance. However, there are many other parameters which are to be considered like access time costs in the aspects of time and energy. Access time is the time required by a processor to access data or to write data from and to memory. Higher performance can be achieved with a reduction of access time costs. So, to decrease the access time and energy consumption, we are proposing an approach for selecting the page to be replaced.

As disk performance continues to lag behind that of memory systems and processors, virtual memory management becomes increasingly important for overall system performance. In this paper we study the page reference behavior of a collection of memory-intensive applications, and propose a new virtual memory page replacement algorithm, SEQ. SEQ detects long sequences of page faults and applies most-recently-used replacement to those sequences. Simulations show that for a large class of applications, SEQ performs close to the optimal replacement algorithm, and significantly better than Least-Recently-Used (LRU). In addition, SEQ performs similarly to LRU for applications that do not exhibit sequential faulting.

Heaps and heapsort on secondary storage

Scientific data files have been increasing in size during the past decades. In the medical field, for instance, magnetic resonance imaging and computer aided tomography can yield image volumes of several gigabytes. While secondary storage (hard disks) increases in capacity and its cost per megabyte slumps over the years, primary memory (RAM) can still be a bottleneck in the processing of huge amounts of data. This represents a problem for image processing algorithms, which often need to keep in memory the original image and a copy of it to store the results. Operating systems optimize memory usage with memory paging and enhanced I/O operations. Although image processing algorithms usually work on neighbouring areas of a pixel, they follow pre-determined paths through the image and might not benefit from the memory paging strategies offered by the operating system, which are general purpose and unidimensional. Having the principles of locality and pre-determined traversal paths in mind, we developed an algorithm that uses multi-threaded pre-fetching of data to build a disk cache in memory. Using the concept of a window that slides over the data, we predict the next block of memory to be read according to the path followed by the algorithm and asynchronously pre-fetch such block before it is actually requested. While other out-of-core techniques reorganize the original file in order to optimize reading, we work directly on the original file. We demonstrate our approach in different applications, each with its own traversal strategy and sliding window structure.

Storage Class Memory(SCM), such as PRAM, FRAM and MRAM, are expected to be comparable to DRAM in terms of access speed and to Flash memory in terms of capacity in a near future. In this paper, assuming that not only the secondary storage (HDD or Flash memory) but also the primary memory (DRAM) will be replaced by SCM in the future computer systems, we propose an efficient file access framework for the SCM based computer systems. The proposed framework do not assign exclusive area in the SCM to the file system and uses various memory-related techniques, such as unified data access path, zero-copy data read using file mapping, copy-on-write, and multiple page pre-faulting for file management. Based on the preliminary experimental results, we could conclude that the proposed framework can be an efficient baseline for designing a new operating system for the SCM based computer systems.