I/O buffer performance in a virtual memory system

The authors have designed and implemented a modular Lisp interpreter for garbage collector evaluation. Data structures such as the list store, the hash table, the symbol table and the stacks were kept in separate modules with only the routines needed to handle them. Routines in other modules may only read and manipulate these data structures through the specified routines. Using this approach, when a garbage collector strategy or method of storing list cells is changed only the store module need be modified. Test programs and measurement strategies were designed for evaluating garbage collector performance in a virtual memory environment. Three garbage collectors have been coded and tested. They are a conventional link reversal marking garbage collector, a conventional recopying garbage collector, and a garbage collector integrated with the system swapper. The implementations are described and their performances are compared. >

With the rapidly growing demands for large capacity main memory in server systems and embedded systems, current DRAM-only approach is hitting the limit due to DRAM's capacity scaling issue and significant background power. With the emergence of new non-volatile memories, or storage-class memories (SCMs), we can now explore low power, high capacity memory subsystem by redesigning virtual memory system to be SCM-aware. Most research on virtual memory system design has focused on minimizing page fault frequency due to slow data transfers using storage such as HDD/SSD as virtual memory swap device. However with an SCM-based swap device, its near-DRAM access latency has potential for reducing requisite DRAM size by aggressively evicting pages from DRAM to SCM without sacrificing performance, and thus reducing background power by powering off the freed DRAM space for low power. To select an optimal SCM from among the many candidate SCM technologies, the impact of SCM characteristics was evaluated using full-system simulation. Results show that utilizing SCM with low access latency and low write energy can lead to significant potential reduction of memory subsystem energy by up to 83%, while maintaining performance degradation within acceptable range.

Sprite is an operating system being designed for a network of powerful personal workstations. A virtual memory system has been designed for Sprite that currently runs on the Sun architecture. This virtual memory system has several important features. First, it allows processes to share memory. Second, it allows all of the physical pages of memory to be in use at the same time; that is, no pool of free pages is required. Third, it performs remote paging. Finally, it speeds program startup by using free memory as a cache for recently-used programs.

Performance analysis of SPMD algorithms on a network of workstations with virtual shared memory

Virtual memory system multiplexes the single physical memory for multiple running processes with two centralized resources, i.e., virtual memory space and page table hierarchy. However, for multithreaded applications running a single address space, current centralized VM system design encounters severe scalability bottlenecks and significantly impedes the application speedup increment on many-core systems. This paper proposes a novel VM system called MedusaVM to scale VM system to many cores. To this end, MedusaVM partitions the global virtual memory space and page table tree in a memory-efficient way, eliminating performance interference and lock contention between cores. Moreover, MedusaVM also provides a traditional shared memory interface for multithreaded applications.

We study algorithms for computing the equijoin of two relations in a system with a standard architecture hut with large amounts of main memory. Our algorithms are especially efficient when the main memory available is a significant fraction of the size of one of the relations to he joined; but they can be applied whenever there is memory equal to approximately the square root of the size of one relation. We present a new algorithm which is a hybrid of two hash-based algorithms and which dominates the other algorithms we present, including sort-merge. Even in a virtual memory environment, the hybrid algorithm dominates all the others we study. Finally, we describe how three popular tools to increase the efficiency of joins, namely filters, Babb arrays, and semijoins, can he grafted onto any of our algorithms.

Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of demand-paged, virtually addressed main memory shared between both of these processing elements. Furthermore, we have achieved low-latency communication between software running on the CPU and the reconfigurable compute unit, allowing even fine-grained hardware/software partitioning. A system-level evaluation quantifies the advantages of our approach.

An analytical study of strategy-oriented restructuring algorithms

The concept of a "working-set" of a program running in a virtual memory environment is now so familiar that many of us fail to realize just how little we really know about what it is, what it means, and what can be done to make such knowledge actually useful. This follows, perhaps, from the abstract and apparently intangible facade that tends to obscure the meaning of working set. What we cannot measure of ten ranks high in curiosity value, but ranks low in pragmatic utility. Where we have measures, as in the page-seconds of SMF/MVS, the situation becomes even more curious: here a single number purports to tell us something about the working set of a program, and maybe something about the working sets of other concurrent programs, but not very much about either.This paper describes a case in which the concept of the elusive working set has been encountered in practice, has been intensively analyzed, and finally, has been confronted in its own realm. It has been trapped, wrapped, and, at last, forced to reveal it self for what it really is. It is not a number! Yet it can be measured. And what it is, together with its measures, turns out to be something not only high in curiosity value, but also something very useful as a means to predict the page faulting behavior of a program running in a relatively complex multiprogrmmed environment.The information presented here relates to experience gained during the conversion of a discrete event simulation model to a hybrid model which employs analytical techniques to forecast the duration of "steady-state" intervals between mix-change events in the simulation of a network-scheduled job stream processing on a 370/168-3AP under MVS. The specific "encounter" with the concept of working sets came about when an analytical treatment of program paging was incorporated into the model. As a result of considerable luck, ingenuity, and brute-force empiricism, the model won.Several examples of empirically derived characteristic working set functions, together with typical model results, are supported with a discussion of relevant modeling techniques and areas of application.

Article Free Access Share on Communication strategies for out-of-core programs on distributed memory machines Authors: Rajesh Bordawekar ECE Dept. and NPAC, Syracuse University, Syracuse, NY ECE Dept. and NPAC, Syracuse University, Syracuse, NYView Profile , Alok Choudhary ECE Dept. and NPAC, Syracuse University, Syracuse, NY ECE Dept. and NPAC, Syracuse University, Syracuse, NYView Profile Authors Info & Claims ICS '95: Proceedings of the 9th international conference on SupercomputingJuly 1995 Pages 395–403https://doi.org/10.1145/224538.224642Published:03 July 1995Publication History 5citation191DownloadsMetricsTotal Citations5Total Downloads191Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Problem statement: To find frequently occurring Sequential patterns f rom web log file on the basis of minimum support provided. We introduced an efficient strategy for discovering Web usage mining is the application of sequential pattern min ing techniques to discover usage patterns from Web data, in order to understand and better serve the n eeds of Web-based applications. Approach: The approaches adopt a divide-and conquer pattern-growth principle. Our proposed method combined tree projection and prefix growth features from pattern- growth category with position coded feature from early-pruning category, all of these features are k ey characteristics of their respective categories, so we consider our proposed method as a pattern growth, early-pruning hybrid algorithm. Results: Our proposed Hybrid algorithm eliminated the need to st ore numerous intermediate WAP trees during mining. Since only the original tree was stored, it drastically cuts off huge memory access costs, which may include disk I/O cost in a virtual memory environment, especially when mining very long sequences with millions of records. Conclusion: An attempt had been made to our approach for improving efficiency. Our proposed method totally e liminates reconstructions of intermediate WAP- trees during mining and considerably reduces execut ion time.

The MULTIPLUS project aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming environment for the MULTIPLUS architecture by providing facilities for the creation of threads, the allocation of private and shared memory space and the efficient use of synchronization primitives. After presenting the main features of the MULTIPLUS architecture and of the MULPLIX operating system, the paper describes in detail the design and the implementation of the three MULTIPLUS architecture basic hardware modules: the Processing Element, the Multistage Interconnection Network and the I/O Processor. In addition, the definition of the MULPLIX parallel programming primitives is discussed and their use is illustrated through an example. Finally, future directions in the development of the MULTIPLUS research project are commented.

Virtual memory systems page out a cluster of contiguous modified pages in virtual memory to a swap disk at one disk I/O but cannot find large clusters in applications mainly changing non-contiguous pages. Our proposal stores small clusters at one disk I/O. This decreases disk writes for paging out small clusters, thus improving page-out performance. key words: virtual memory system, page-out, page clustering, disk

This paper describes applications uses of a novel memory model and an attendant architectural support that incorporate the new emphases in operating system and hardware design. A major contribution of the model is that various access control protocols can be supported directly by the virtual memory system. In the past, specialized, dedicated hardware support was developed for memory management subsystems in order to support specific protocols. This work promotes multifunctionality in that the kernel and its supporting hardware can be configured with different rules and used through a simple virtual memory primitive call. The class of protocols which can be supported is defined at a high level of abstraction by constraints on the protection system state representation and transitions performed by Finite State Machines. Illustration of the applications uses of the model are given in the context of various coherence control protocols and a Mach 3.0 user-level pager thus demonstrating the model's flexibility in the provision of a wide range of choices to users.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The computer programmer write programming codes of any length without keeping in mind the available primary memory. This is possible if we use the concept of virtual memory. As the name suggests, virtual memory is a concept of executing a programming code of any size even having a primary memory of smaller size than the size of program to be executed. The virtual memory can be implemented using the concept of paging. The operating system allocates a number of memory frames to each program while loading into the memory. The programming code is equally divided into pages of same size as frame size. The size of pages and memory frames are retained equal for the better utilization of the memory. During the execution of program, every process is allocated limited number of memory frames; hence there is a need of page replacements. To overcome this limitation, a number of page replacement techniques had suggested by the researchers. In this paper, we have proposed an modified page replacement technique, which is based on the concept of block reading of pages from the secondary storage. The disc access is very slow as compared to the access from primary memory. Whenever there is a page fault, the required page is retrived from the secondary storage. The numerous page faults increase the execution time of process. In the proposed methodology, a number of pages, which is equal to the allotted memory frames, are read every time when there is a page fault instead of reading a single page at a time. If a block of pages has fetched from secondary storage, it will definitely increases the possibilities of page hit and as a result, it will improve the hit ratio for the processes.