An Improved Research on Frequency-Fixed Cascaded SOGI Single-Phase PLL

Suppressing the negative effects of grid voltage harmonics on the estimated frequency of a phase-locked loop (PLL) is a challenge in literature. This article proposes an easy-to-implement quadrature signal generator (QSG) to attenuate the oscillations on the estimated frequency in single-phase grid-connected inverters, which use second-order generalized integrator (SOGI)-PLL. It is shown that SOGI exerts a stronger filtering effect in generating the quadrature signal than the in-phase signal. Against this background, in this work, a modified integrator is introduced into the path of the in-quadrature signal to generate another in-phase component with much lower harmonic content. The proposed method imposes only a small computational burden on the existing SOGI-PLL compared to the previously presented methods that address the input voltage harmonic problem. Moreover, this method can work properly within the allowable range of grid voltage frequency deviations. The proposed integrator benefits from an error-decaying mechanism to overcome dc drift in pure integrators. The integrator has been designed based on theoretical equations. The validity of the proposed QSG and theoretical equations is evaluated using simulations and experimental studies. A fixed-point representation of the proposed QSG is also provided for implementation on low-cost microcontrollers.

This paper presents an accurate technique for the estimation of single-phase grid voltage fundamental amplitude and frequency. The technique consists of a quadrature signal generator (QSG) and a discrete Fourier transform (DFT). The frequency information required by the QSG based on a second-order generalized integrator (SOGI) is estimated using the spectral leakage property of the DFT. The presented DFT operation does not require real-time evaluation of trigonometric functions. The frequency estimation is less affected by the presence of harmonics when compared to similar techniques based on QSG-SOGI such as the phase-locked loop and the frequency-locked loop. Moreover, unlike these techniques, the DFT-based QSG-SOGI (DFT-SOGI) technique does not create any interdependent loops, thus increasing the overall stability and easing the tuning process. The effectiveness of the proposed technique has been validated on a real-time experimental setup.

Conventional back-EMF based sensorless control methods suffer the harmonic fluctuation of position estimation owing to the 5th and 7th current harmonics brought by the inverter nonlinearities. In this paper, a linear extended state observer (LESO)-based position estimation method with an improved phase-locked loop (PLL) is proposed to eliminate the harmonic fluctuation. Two LESOs provide the chattering-free estimation of back-electromotive force (EMF) for both α-and β-axis. A second-order generalized integrator (SOGI) is incorporated into the conventional PLL, thus eliminating the 6th harmonic component of the position estimation error in the feedforward path of the PLL. Compared with the state-of-art proposals, which normally utilize at least four SOGIs or other kinds adaptive filters to eliminate the 5th and 7th harmonics of the estimated back-EMF for both α- and β-axis, the proposed method only employs one SOGI while still holds a good position error harmonics elimination performance. In this way, the system complexity and computational burden can be significantly reduced. Simulation results confirm the effectiveness of the proposed method.

In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid voltage is under unbalanced and distorted conditions. Many filtering techniques are utilized to solve this problem, however, at the cost of slowing down the transient response. It is a major challenge for PLL to achieve a satisfactory dynamic performance without degrading its filtering capability. To tackle this challenge, a hybrid filtering technique is proposed in this paper. Our idea is to eliminate the fundamental frequency negative sequence (FFNS) and other harmonic sequences at the prefiltering stage and inner loop of PLL, respectively. Second-order generalized integrators (SOGIs) are used to remove FFNS before the Park transformation. This makes moving average filters (MAFs) eliminate other harmonics with a narrowed window length, which means the time delay that is caused by MAFs is reduced. The entire hybrid filtering technique is included in a quasi-type-1 PLL structure (QT1-PLL), which can provide a rapid dynamic behavior. The small-signal model of the proposed PLL is established. Based on this model, the parameter design guidelines targeting the fast transient response are given. Comprehensive experiments are carried out to confirm the effectiveness of our method. The results show that the settling time of the proposed PLL is less than one grid cycle, which is shorter than most of the widespread PLLs. The harmonic rejection capability is also better than other methods, under both nominal and adverse grid conditions.

Dual quadrature signal generator (QSG) along with a positive sequence calculator (PSC) eliminates the negative sequence components from unbalanced grid voltages. The QSGs also offer attenuation to harmonics and dc-offset present in the sensed input voltages. Fourth-order QSGs offer superior harmonic attenuation with complete dc-offset rejection compared to lower-order QSGs. Therefore, dual fourth-order QSG + PSC is an apt solution for pre-filtering in phase-locked loops (PLLs) under non-ideal grid voltage conditions. Two fourth-order QSGs (FO-QSGs) namely, second-order SOGI-QSG (SO-SOGI-QSG) and cascaded SOGI-QSG have been proposed in the literature. Parameter selection for these FO-QSGs to achieve a faster dynamic response is challenging due to the higher order of the transfer functions. The response time of the QSGs directly impact the response time of the PLL. This paper proposes a new approach to fourth-order quadrature signal generation that achieves a lower settling time for the QSG compared to existing FO-QSGs. The proposed method achieves a faster response time by setting the QSG parameters using equations that directly relate to the system settling time. Using the proposed method, the QSG settles within 25.4 ms while maintaining a low total harmonic distortion.

It is a major challenge for the grid-connected power electronic converter circuits to get synchronized with the utility grid when the grid voltage is highly unbalanced and polluted with harmonics. In this situation designing a phase lock loop (PLL) is a challenge to estimate the phase, frequency, and amplitude of the utility voltage. Phase lock loop (PLLs) is a closed-loop synchronization structure where the error signal is generated from the difference of estimated phases and the reference phase values. This paper presents a filtering technique based on adaptive filter called second-order generalized integrator (SOGI). Under transient fault condition when the three-phase grid signal is highly polluted with harmonics and sudden frequency change or voltage dip occurs, it is a critical task to extract the fundamental component of the grid signal. Here for the extraction of the fundamental component from the polluted signal, two adaptive filters using SOGI can be implemented on the stationary αβ reference frame. To analyze the disturbance rejection capability of the SOGI filter different distortions have been introduced in the three-phase grid signal and the robustness is estimated on the basis of its transient response and harmonic analysis. The simulation results will validate the excellent performance of the filter.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

An improved second order generalized integrators phase locked loop for flexible DC transmission

The precise calculation of phase angle, voltage magnitude and frequency is crucial for the effective control of power electronic inverters connected to an electrical power system. The phase-locked loop (PLL) is a commonly employed method for measuring these variables. Nevertheless, the reliability of this measurement is influenced by transient events in the electrical power system and varies depending on the nature of the event and the specific design of the PLL. Notably, PLLs utilizing the double second-order generalized integrator are widely adopted for power converter synchronization purposes. This article proposes a three-phase PLL, which is based on the single-phase version previously reported by the authors. The proposed PLL, based on an alternative integrator approach, allows a fine adjustment of the tolerance to disturbances in the input voltage thanks to a second feedback gain in its pre-filter. It is reasonable to anticipate that the three-phase PLL will exhibit similar strengths to the single-phase version; however, in the three-phase case, an additional integrator is involved in pre-filtering the quadrature signals, and the double integrator is not employed as the quadrature signal generator. The performance of the proposed PLL is assessed by comparing it to other PLLs based on the second-order integrator, using a processor-in-the-loop approach.

Introduction Frequency synthesizers are pervasively utilized in almost every electronic system for generation of the well-defined clock frequencies of interest. For instance, in the modern wireless transceiver, a phase-locked loop (PLL) is commonly used to generate RF frequencies to up-convert and down-convert the analog signal. On the baseband side, the mixed-signal circuit, such as switched-capacitor filters, as well as digital VLSI also require PLLs to synthesize various clock domains. Moreover, the trend of future electronic design will continue to integrate more functionality, support multiple standards, and multi-channels in a system-on-chip (SoC) platform, which will inevitably increase the number of frequency synthesizers for various analog and digital circuit blocks. As a result, minimizing the power and area consumption of a frequency synthesizer becomes increasingly critical, or it can become the dominant cost factor in the overall system. This system trend has been driving PLL design towards more reconfigurability, wider tuning range and lower cost. The digitally-assisted PLL design concept becomes a natural consequence of this trend, as the flexibility offered via digital means is always appealing. Conventionally, the frequency synthesizer is implemented using an analog approach, i.e., the charge-pump PLL, as shown in Figure 4.1(a). The basic operation of this type of PLL has been well documented in textbooks and the literature [1, 2]. In brief, it processes the phase information in the analog domain via a phase frequency detector and a charge-pump circuit, so that the phase difference turns into current pulses. This current signal is then converted into voltage form via the analog loop filter, which typically consists of capacitor and resistor array. Some degree of digitally-assisted concept was adopted for this type of PLL, mainly to digitally reconfigure the analog loop filter and voltage-controlled oscillator (VCO). For example, the PLL may be required to support different PLL loop bandwidths and/or a wide VCO tuning range. The digitally switched capacitor or resistor bank is a common choice to support this kind of operation. While this analog PLL topology has been widely adopted and proven in both the literature and commercial products, it presents a challenge to scale with technology. The analog loop filter is typically composed of bulky passive components whose values are determined by the desirable PLL loop bandwidth, and cannot be arbitrarily reduced.

This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based on a All-Pass Filter (APF) with Lattice structure. Both methods are very attractive because of their simple digital implementation, low computational load and good performance under harmonically distorted grid conditions and variable frequency, so they are a good alternative to other known methods. The paper derives and analyzes the full state space models of the two methods.It is shown that these two methods are equivalent in the most common operation conditions of distributed energy resources, although the APF structure is clearly better than the SOGI one because it maintains its orthogonal generation ability for any higher notch frequencies and any lower sampling frequencies. The comparative analysis were validated by simulation with MATLAB/Simulink and experimental results using a fixed-point DSP.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

This paper proposes the application of frequency locked loop (FLL) based on the second order generalized integrator (SOGI) and a Kalman filter (KF) for frequency adaptive instantaneous power quality (PQ) analysis. The FLL tracks the time-varying grid voltage fundamental frequency adaptively. The orthogonal waveforms of fundamental and harmonic components of grid voltage waveform are extracted using the quadrature signal generator (QSG)-SOGI and a linear Kalman filter (LKF), respectively. The fundamental voltage amplitude is obtained from the orthogonal voltage waveforms as provided by the QSG-SOGI and is fed to an extended Kalman filter (EKF) to extract the instantaneous flicker level (IFL). The proposed SOGI-FLL-KF technique provides accurate instantaneous results for PQ analysis based on the measurement of phasor quantities. Synthetically generated grid voltage waveforms are used in MATLAB/Simulink for instantaneous PQ analysis by the proposed SOGI-FLL-KF technique. The simulation results show that the proposed technique can be used as an effective technique for frequency adaptive instantaneous PQ assessment.

Synchronization unit such as single-phase grid voltage phase-locked loop (PLL) is essential to control scheme in single-phase converters. However, the design of PLL is not simple and increases the complexity of control system, and the performance of PLL could be impacted by the waveform quality of the main voltage. Therefore, in this paper, a novel single-phase power calculation method without PLL is proposed to improve the performance of single-phase three-level rectifier which is widely used in railway traction drive system. Moreover, a strategy to compensate phase angle and power calculation error is presented to improve the power calculation precision and enlarge operation range. Then the compensation strategy and the single-phase power calculation method are combined with a common direct power control (DPC) to form a no-PLL control system for single-phase three-level rectifiers. Finally, performance of the proposed scheme is verified through experimental tests and compared with two traditional PLL-based control schemes.

To address the problem of reduced estimation accuracy in sensorless control of permanent magnet synchronous motor (PMSM) at low speeds, caused by signal delay and additional noise introduced by conventional filters used for extracting high-frequency (HF) signals, this paper presents a sensorless control strategy for PMSM in the low-speed region based on the second-order generalized integrator (SOGI). Within this study, a method based on HF voltage injection is employed to excite current responses containing rotor position (RP). To effectively extract these HF current components, a SOGI is utilized in the signal processing stage. Moreover, a Phase-Locked Loop (PLL) is integrated into the RP estimation algorithm to enhance noise suppression and improve estimation accuracy. Results obtained from experiments demonstrate that, in comparison to conventional methodologies, the put-forward control strategy substantially improves the RP estimation accuracy in low-speed regimes operating conditions while maintaining system stability. This provides an effective solution to the key technical challenges in low-speed region sensorless control of PMSM.