An inter-device communication protocol for modular smart-objects

To address the limitations of existing IoT edge nodes—such as poor scalability, limited hardware interchangeability, and high customization costs—this paper proposes a modular edge node design based on the SPI (Serial Peripheral Interface) bus. The system employs a multi-processor architecture and uses the SPI bus as a backbone for modular expansion. By adopting a “standard access–terminal adaptation” strategy and a protocol-transparent transmission mechanism, the design achieves hardware unification, flexible device access, and general interchangeability. A unified transparent transmission frame format is used for data encapsulation and forwarding, effectively resolving compatibility issues caused by heterogeneous interfaces and protocols. Practical applications demonstrate that the proposed design significantly enhances the flexibility and scalability of edge nodes while reducing deployment and maintenance costs, demonstrating high practical value in engineering applications.

Chapter 12 - SPI Communication

A local sensor bus for transmitting data from several digital smart sensors to an Internet interface was tested. The master/slave type bus is based on the three-wire SPI (serial peripheral interface) bus, which is built into most microcontrollers. At the sensor end, after A/D conversion of the analog sensor signals and further processing of the digitized data, the data is formatted into standard 8-byte ASCII code, which can be read directly by any computer. A header indicates the type of sensor data, for example, TC123.45 for a temperature sensor reading 123.45/spl deg/C. The data is in the form of an email so the following Internet interface (TCP/IP) only retransmits the data to the requesting browser where it is displayed in the same format as any email The Esbus format consists of an 8-byte request from the master followed by 32-byte response from the selected slave. The response is subdivided into an 8-byte header, which identifies the sensor and channel number, and three sets of 8-byte sensor data, as described above. In order to adapt the SPI an addressable network, the data output driver is converted to open collector. The paper will describe the I/O circuits, waveform/timing, and data formats for a specific smart sensor (temperature, humidity, illumination).

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

CHAPTER 7 - Serial Peripheral Interface Bus Operation

Serial Peripheral Interface (SPI) is a commonly used communication protocol that allows serial data transfer between a master and a slave device over a short distance. However, the current implementation of the Serial Peripheral Interface has a low speed and clock synchronization issue. When it comes to automotive, there a few things that are needed to be taken into consideration to increase the performance of the interface device. The paper present the design, simulation, verification and optimize SPI based on automotive interface device specifications. This includes a higher speed for the interface device and the efficiency of power dissipation. The SPI has been successfully optimized with a 1000MHz speed, a power of $575.7694 \mu \mathrm{W}$ and a total area of 1102.81mm2. The speed and area achieved are well improved over the current design of SPI. Even though the total dissipation achieved is above the current implemented SPI design, it is acceptable due to the technical relation between power and speed in VLSI design.

Synchronous serial interfaces are frequently employed to offer cost-effective board-level interfaces between various devices, including microcontrollers, DACs, ADCs, and others. Components that are compatible with SPI and Microwire are made by numerous IC makers. An interface called Serial Peripheral Interface (SPI) makes it easier to send synchronous serial data. In master/slave mode, data frames are initiated by the master device. With a separate slave choose line, multiple slave devices are permitted. It is necessary to guarantee that the given hardware design operates as intended and produces the desired outcomes. The design phases would need to be repeated after the functional flaws were discovered. Verification is thus a process that is time and money efficient. Due to this, a strong testbench structure is required, one that includes large broad verification elements that are easily extensible across designs and are extensively reusable. To gain good control over stimulus creation, functional coverage, and other factors, an industry standard verification technique is needed. The primary goal of this work is to design the Master SPI Core and use System Verilog to validate the code. Serial Peripheral Interface of symmetrical structure was synthesized using Cadence genus, and then simulated using Questa IDE. The testing of the SPI core was done by inserting the scan chains using the Cadence Genus tool and finally the code coverage of the SPI core was captured using the Questa IDE. Keywords: SPI, Coverage, Protocol, I2C, Functional Verification

The Internet of Things (IoTs) is a network of interconnected devices, transportations, home appliances, and other devices. They are functionally embedded in electronics, software, sensors, actuators, and connectivity that allows them to connect and exchange information. On the basis of the IoT concept, implementations are gradually being proposed in a range of areas, ranging from smart house, smart office and smart agriculture. In this research paper, a generic framework for smart monitoring applications based on the IoTs network is proposed. In this framework, low-powered sensor nodes are based on the micro:bit platform, providing a multiple footprints for different sensor connections. The wireless capability on micro:bit provides a complete solution to deploy the system in such places that wire is impractical to draw. The data is wirelessly gathered by a basestation node that is powered by Android Things operating system provided by Google. This operating system is based on the Android platform for smart devices and Internet of Things products. The approach to this framework indicates a low cost and minimum setup and especially amenable for applications control. To support many applications with minimum modifications, the framework is designed for easy expansion by supporting popular serial connection ports, including the Universal Asynchronous Receiver/Transmitter and Serial Peripheral Interface. With these connections, on one line data bus, several sensors can be added to match the different application requirements. In this paper, our platform is validated for an automatic water monitoring in aquaculture based on the temperature, pH and dissolved oxygen sensory data. Through our framework, the data is uploaded to a cloud for remote monitoring and providing alarms for users whenever the data is out of a predefined safe domain.

The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol commonly used in embedded systems, facilitating the connection between microcontrollers and peripheral devices such as sensors, displays, and memory. Traditional SPI hardware implementations often lack flexibility in clock frequency, clock polarity (CPOL), and clock phase (CPHA), limiting their adaptability in various applications and increasing development time and cost. To address these issues, this study designs and implements a configurable SPI module that can dynamically adjust parameters such as clock frequency, data bit width, CPOL, and CPHA through register control. The core of this design adopts a modular architecture that allows flexible configuration via register control, ensuring compatibility with different SPI modes and peripheral devices. Simulation tests have verified that the SPI module achieves the expected dynamic flexibility across multiple operation modes while ensuring communication accuracy and system stability.The configurable SPI module enhances the adaptability of embedded system communication protocols, reducing the need for hardware redesigns for specific applications. This register-based dynamic SPI design holds significant practical value in engineering applications and helps improve hardware development efficiency.

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- μW 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

The current massive use of digital communications demands a secure link by using an embedded system (ES) with data encryption at the protocol level. The serial peripheral interface (SPI) protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Henon map and two methods for blur and permute (in combination with DNA sequences). The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.

This paper presents an incremental optical encoder based position and velocity measurements VLSI chip with a serial peripheral interface (SPI). It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range. By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. Furthermore, multiple copies of the velocity encoder can access the behavior of multiple motors in parallel. It is compact with lower power consumption compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3M <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5μm</i> CMOS process and consumes 4.82mW power with active area of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45mm²</i> .

A wide speed range and high precision position and velocity measurements chip with serial peripheral interface

Since the Internet of Things (IoT) will be entwined with everything we use in our daily life, the consequence of security flaws escalates. Smart objects will govern most of the home appliances and car engines yielding potential disaster scenarios. In this context, successful attacks could lead to chaos and scary scenarios (www.darkreading.com). Unprotected personal information may expose sensitive and embarrassing data to the public and attacks may threaten not only our computers and smart devices, but our intimacy and perhaps our lives too. Because persons and objects will be bonded with each other, user consent becomes critical. Therefore, thing, object, and user Identity will be the focus of future IoT security solutions, yielding a Trust, Security, and Privacy (TSP) paradigm, which may constitute the Achilles' heel of IoT. While security issues are quite straightforward, mainly from background knowledge, privacy issues are far more complex. Privacy constitutes a rather challenging task, even for the m...

Overview of the mobility related security challenges in LPWANs