Esbus - a sensor bus based on the SPI serial interface

To address the limitations of existing IoT edge nodes—such as poor scalability, limited hardware interchangeability, and high customization costs—this paper proposes a modular edge node design based on the SPI (Serial Peripheral Interface) bus. The system employs a multi-processor architecture and uses the SPI bus as a backbone for modular expansion. By adopting a “standard access–terminal adaptation” strategy and a protocol-transparent transmission mechanism, the design achieves hardware unification, flexible device access, and general interchangeability. A unified transparent transmission frame format is used for data encapsulation and forwarding, effectively resolving compatibility issues caused by heterogeneous interfaces and protocols. Practical applications demonstrate that the proposed design significantly enhances the flexibility and scalability of edge nodes while reducing deployment and maintenance costs, demonstrating high practical value in engineering applications.

Chapter 12 - SPI Communication

Serial Peripheral Interface (SPI) is a commonly used communication protocol that allows serial data transfer between a master and a slave device over a short distance. However, the current implementation of the Serial Peripheral Interface has a low speed and clock synchronization issue. When it comes to automotive, there a few things that are needed to be taken into consideration to increase the performance of the interface device. The paper present the design, simulation, verification and optimize SPI based on automotive interface device specifications. This includes a higher speed for the interface device and the efficiency of power dissipation. The SPI has been successfully optimized with a 1000MHz speed, a power of $575.7694 \mu \mathrm{W}$ and a total area of 1102.81mm2. The speed and area achieved are well improved over the current design of SPI. Even though the total dissipation achieved is above the current implemented SPI design, it is acceptable due to the technical relation between power and speed in VLSI design.

Synchronous serial interfaces are frequently employed to offer cost-effective board-level interfaces between various devices, including microcontrollers, DACs, ADCs, and others. Components that are compatible with SPI and Microwire are made by numerous IC makers. An interface called Serial Peripheral Interface (SPI) makes it easier to send synchronous serial data. In master/slave mode, data frames are initiated by the master device. With a separate slave choose line, multiple slave devices are permitted. It is necessary to guarantee that the given hardware design operates as intended and produces the desired outcomes. The design phases would need to be repeated after the functional flaws were discovered. Verification is thus a process that is time and money efficient. Due to this, a strong testbench structure is required, one that includes large broad verification elements that are easily extensible across designs and are extensively reusable. To gain good control over stimulus creation, functional coverage, and other factors, an industry standard verification technique is needed. The primary goal of this work is to design the Master SPI Core and use System Verilog to validate the code. Serial Peripheral Interface of symmetrical structure was synthesized using Cadence genus, and then simulated using Questa IDE. The testing of the SPI core was done by inserting the scan chains using the Cadence Genus tool and finally the code coverage of the SPI core was captured using the Questa IDE. Keywords: SPI, Coverage, Protocol, I2C, Functional Verification

CHAPTER 7 - Serial Peripheral Interface Bus Operation

The ability to gather and analyze distributed data adding value to extracted information is a core concept in the Internet of Things. Smart-Objects with multi-sensor capability further enhance environmental awareness with coherent and meaningful information. In this paper we first investigate a modular architecture for multi-sensors Smart-Objects allowing to ease their customization and maintainability. Then, we introduce and detail an efficient and flexible inter-device communication protocol: flexSPI. Built on top of Serial Peripheral Interface (SPI), the proposed approach allows reducing routing overhead and enabling modularity by exploiting packet-oriented messaging. To achieve these improvements, SPI bus is completely shared between connected devices avoiding conflicts by keeping free (i.e. in input direction) the Slave Output/Master Input SOMI signal and occupying it only after proper, advanced addressing. Low power and high bandwidth characteristics of SPI bus are maintained while enabling smart features such as hotpluggability, link diagnosis, devices discovery, synchronization and master solicitation.

In this paper we report the characterizations results of serial peripheral interface (SPI) timing parameters for optical mouse sensor. SPI is an interface that facilitates the transfer of synchronous serial data. It supports two-way communication between mouse sensor and microcontroller. The test setups were used consist of digital oscilloscope, power supply, mouse sensor, test board and personal computer. The SPI timing parameters that were evaluated are read- address data delay, the timing between read and subsequent commands, rise and fall time, hold time, setup time, NCS to SCLK active, SCLK to NCS inactive (read operation) and SCLK to NCS inactive (write operation). The timing parameters results were within the limit as specified in product datasheet.

The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol commonly used in embedded systems, facilitating the connection between microcontrollers and peripheral devices such as sensors, displays, and memory. Traditional SPI hardware implementations often lack flexibility in clock frequency, clock polarity (CPOL), and clock phase (CPHA), limiting their adaptability in various applications and increasing development time and cost. To address these issues, this study designs and implements a configurable SPI module that can dynamically adjust parameters such as clock frequency, data bit width, CPOL, and CPHA through register control. The core of this design adopts a modular architecture that allows flexible configuration via register control, ensuring compatibility with different SPI modes and peripheral devices. Simulation tests have verified that the SPI module achieves the expected dynamic flexibility across multiple operation modes while ensuring communication accuracy and system stability.The configurable SPI module enhances the adaptability of embedded system communication protocols, reducing the need for hardware redesigns for specific applications. This register-based dynamic SPI design holds significant practical value in engineering applications and helps improve hardware development efficiency.

An iridium communications and navigation module (ICNM) has been developed for movement tracking applications. External interfaces to the ICNM include Ethernet, RS-232, and Serial Peripheral Interface (SPI) Bus. The module is powered by Power over Ethernet (PoE) or a +24VDC connection. The ICNM fits within the standard PC104 form factor, but utilizes a Modular Component and Sensor Bus (MCSB) interface specification for the high density connector. The ICNM includes a GPS receiver and accelerators for satellite and inertial tracking. The module manages all of the satellite communication control, encryption, and navigation functions that enable its rapid integration as a component into larger systems.

The current massive use of digital communications demands a secure link by using an embedded system (ES) with data encryption at the protocol level. The serial peripheral interface (SPI) protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Henon map and two methods for blur and permute (in combination with DNA sequences). The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.

Purpose – Behavioral pattern mining for intelligent system such as SmEs sensor data are vitally important in many applications and performance optimizations. Sensor pattern mining (SPM) is also dynamic and a hot research issue to pervasive and ubiquitous of smart technologies toward improving human life. However, in large-scale sensor data, exploring and mining pattern, which leads to detect the abnormal behavior is challenging. The paper aims to discuss these issues. Design/methodology/approach – Sensor data are complex and multivariate, for example, which data captured by the sensors, how it is precise, what properties are recorded or measured, are important research issues. Therefore, the method, the authors proposed Sequential Data Mining (SDM) approach to explore pattern behaviors toward detecting abnormal patterns for smart space fault diagnosis and performance optimization in the intelligent world. Sensor data types, modeling, descriptions and SPM techniques are discussed in depth using real sensor data sets. Findings – The outcome of the paper is measured as introducing a novel idea how SDM technique’s scale-up to sensor data pattern mining. In the paper, the approach and technicality of the sensor data pattern analyzed, and finally the pattern behaviors detected or segmented as normal and abnormal patterns. Originality/value – The paper is focussed on sensor data behavioral patterns for fault diagnosis and performance optimizations. It is other ways of knowledge extraction from the anomaly of sensor data (observation records), which is pertinent to adopt in many intelligent systems applications, including safety and security, efficiency, and other advantages as the consideration of the real-world problems.

This paper presents an incremental optical encoder based position and velocity measurements VLSI chip with a serial peripheral interface (SPI). It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range. By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. Furthermore, multiple copies of the velocity encoder can access the behavior of multiple motors in parallel. It is compact with lower power consumption compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3M <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5μm</i> CMOS process and consumes 4.82mW power with active area of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45mm²</i> .

A wide speed range and high precision position and velocity measurements chip with serial peripheral interface

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.