An interactive visualization for message sequence charts

Networks of Hybrid Automata are a clean modelling framework for complex systems with discrete and continuous dynamics. Message Sequence Charts (MSCs) are a consolidated language to describe desired behaviors of a network of interacting components. Techniques to analyze the feasibility of an MSC over a given HA network are based on specialized bounded model checking techniques, and focus on efficiently constructing traces of the network that witness the MSC behavior. Unfortunately, these techniques are unable to deal with the “unfeasibility” of the MSC, i.e. that no trace of the network satisfies the MSC. In this paper, we tackle the problem of MSC unfeasibility: first, we propose specialized techniques to prove that an MSC can not be satisfied by any trace of a given HA network; second, we show how to explain why an MSC is unfeasible. The approach is cast in an SMT-based verification framework, using a local time semantics, where the timescales of the automata in the network are synchronized upon shared events. In order to prove unfeasibility, we generalize k-induction to deal with the structure of the MSC, so that the simple path condition is localized to each fragment of the MSC. The explanations are provided as formulas in the variables representing the time points of the events of the MSCs, and are generated using unsatisfiable core extraction and interpolation. An experimental evaluation demonstrates the effectiveness of the approach in proving unfeasibility, and the adequacy of the automatically generated explanations.

Message Sequence Charts (MSCs) is a standardized visual notation for expressing requirements in communicating systems. MSCs are commonly used to specify scenarios describing message exchange among entities such as objects, components, systems, etc. A multiplicity is a modeling construct that is used to define constraints in the existential relationships between entities and it is frequently found in static models, such as class or entity diagrams. This paper describes a formal approach for formalizing the combination of MSCs with multiplicities. The formalization is achieved by defining an instantiation partial function that provides a clear interpretation of how to instantiate MSCs with multiplicities. The formalization uses composition operators that are used to formalize inline expressions (a well-known MSCs modeling construct). This formalization is designed to allow integration with the current formal semantics proposed for MSCs

Message Sequence Charts (MSCs) are an attractive visual formalism<br /> widely used to capture system requirements during the early<br />design stages in domains such as telecommunication software. It is<br />fruitful to have mechanisms for specifying and reasoning about <br />collections of MSCs so that errors can be detected even at the requirements<br /> level. We propose, accordingly, a notion of regularity for <br />collections of MSCs and explore its basic properties. In particular, we<br />provide an automata-theoretic characterization of regular MSC <br />languages in terms of finite-state distributed automata called bounded<br />message-passing automata. These automata consist of a set of <br />sequential processes that communicate with each other by sending and<br />receiving messages over bounded FIFO channels. We also provide a<br />logical characterization in terms of a natural monadic second-order<br />logic interpreted over MSCs.<br />A commonly used technique to generate a collection of MSCs is<br />to use a Message Sequence Graph (MSG). We show that the class of<br />languages arising from the so-called locally synchronized MSGs constitute<br /> a proper subclass of the languages which are regular in our sense.<br />In fact, we characterize the locally synchronized MSG languages as<br />the subclass of regular MSC languages that are finitely generated.

A message sequence chart (MSC) is a standard notation for describing the interaction between communicating objects. It is popular among the designers of communication protocols. MSCs enjoy both a visual and a textual representation. High-level MSCs (HMSCs) allow specifying infinite scenarios and different choices. Specifically, an HMSC consists of a graph, where each node is a finite MSC with matched send and receive events, and vice versa. In this paper we demonstrate a weakness of HMSCs, which disallows one to model certain interactions. We will show, by means of an example, that some simple finite state communication protocol cannot be represented using HMSCs. We then propose an extension to the MSC standard which allows HMSC nodes to include unmatched messages. The corresponding graph notation will be called HCMSC, which stands for high-level Compositional message sequence charts. With the extended framework, we provide an algorithm for automatically constructing an MSC representation for finite state asynchronous message passing protocols.

Message sequence charts (MSCs) is a standard notation for describing the interaction between communicating objects. It is popular among the designers of communication protocols. MSCs enjoy both a visual and a textual representation. High level MSCs (HMSCs) allow specifying infinite scenarios and different choices. Specifically, an HMSC consists of a graph, where each node is a finite MSC with matched send and receive events, and vice versa. In this paper we demonstrate a weakness of HMSCs, which disallows one to model certain interactions. We will show, by means of an example, that some simple finite state and simple communication protocol cannot be represented using HMSCs. We then propose an extension to the MSC standard, which allows HMSC nodes to include unmatched messages. The corresponding graph notation will be called HCMSC, which stands for High level Compositional Message Sequence Charts. With the extended framework, we provide an algorithm for automatically constructing an MSC representation for finite state asynchronous message passing protocols.

We study the notion of safe realizability and implied scenarios for Message Sequence Chart (MSC) specifications with the following contributions: (1) We investigate the cause of implied scenarios and show that even though implied scenarios are an artifact of the distributed and global system behaviour, nevertheless, they are the result of the nondeterminism in the local behaviour of processes, (2) Instead of deadlock states and safe realizability for MSC specifications, we introduce the notions of stuck states and strong safe realizability. Moreover, we use emergent scenarios to name both implied scenarios and those anomalies of MSC specifications that are captured by the notion of strong safe realizability, (3) We give an algorithm that reduces strong safe realizability (or safe realizability) of MSC specifications to strong safe realizability (or safe realizability) of a set of MSCs.

Message Sequence Charts (MSC) have been traditionally used to depict execution scenarios in the early stages of design cycle. MSCs portray inter-object interactions. Synthesizing intra-object executable specifications from an MSC-based description is a non-trivial task. Here we present a model of computation called Communicating Transaction Processes (CTP) based on MSCs from which an executable specification can be extracted in a straightforward manner. Our model describes a network of communicating processes in which the processes interact via common action labels. Each action is a non-atomic interaction described as a guarded choice of MSCs. Thus our model achieves a separation of concerns: the high-level network of processes depicting intra-process computations and control flow, while the common non-atomic communication actions capture inter-process interaction viaMSCs. We show how to extract an ordinary Petri net from a CTP model thereby leading to a standard operational semantics. We also discuss the connection of our formalism to Live Sequence Charts, an extension of MSCs which also has an executable semantics.

Message sequence charts (MSCs) are commonly used to specify interactions between agents in communicating systems. Their visual nature makes them attractive for describing scenarios, but also leads to ambiguities that can result in incomplete or inconsistent descriptions. One such problem is that of implied scenarios—a set of MSCs may imply new MSCs which are “locally consistent” with the given set. If local consistency is defined in terms of local projections of actions along each process, it is undecidable whether a set of MSCs is closed with respect to implied scenarios, even for regular MSC languages [3]. We introduce a new and natural notion of local consistency called causal closure, based on the causal view of a process—all the information it collects, directly or indirectly, through its actions. Our main result is that checking whether a set of MSCs is closed with respect to implied scenarios modulo causal closure is decidable for regular MSC languages.

In testing systems with distributed interfaces/ports, we may place a separate tester at each port. It is known that this approach can introduce <it>controllability problems</it> which have received much attention in testing from finite state machines. Message sequence charts (MSCs) form an alternative, commonly used, language for modelling distributed systems. However, controllability problems in testing from MSCs have not been thoroughly investigated. In this paper, controllability problems in MSC test cases are analysed with three notions of observability: local, tester and global. We identify two types of controllability problem in MSC-based testing. It transpires that each type of controllability problem is related to a type of MSC pathology. <it>Controllability problems of timing</it> are caused by races but not every race causes controllability problems; <it>controllability problems of choice</it> are caused by non-local choices and not every non-local choice causes controllability problems. We show that some controllability problems of timing are avoidable and some controllability problems of choice can be overcome when testers have better observational power. Algorithms are provided to tackle both types of controllability problems. Finally, we show how one can overcome controllability problems using a coordination service with status messages based on algorithms developed in this paper.

Message Sequence Charts (MSCs) is a visual formalism for the descrip- tion of communication behaviour of distributed systems. An MSC specifies relations between communication events with partial orders. A situation when two visually ordered events may occur in any order during an execution of an MSC is called a race and is usually considered as a design error. While there is a quadratic time al- gorithm detecting races in a finite communication behaviours called Basic Message Sequence Charts (BMSCs), the race detection problem is undecidable for High-level Message Sequence Charts (HMSCs), an MSC formalism describing potentially infi- nite sets of potentially unbounded behaviours. To improve this negative situation for HMSCs, we introduce two new notions: a new concept of race called trace-race and an extension of the HMSC formalism with open coregions, i.e. coregions that can extend over more than one BMSC. We present three arguments showing benefits of our notions over the standard notions of race and HMSC. First, every trace-race-free HMSC is also race-free. Second, every race-free HMSC can be equivalently ex- pressed as a trace-race-free HMSC with open coregions. Last, the trace-race detec- tion problem for HMSC with open coregions is decidable and PSPACE-complete. Finally, the proposed extension of coregions allows to represent in a visual fash- ion whether an arbitrary number of racing events in the usual MSC formalism are concurrent or not.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

Message sequence charts (MSC) are widely used in the early design of communication protocols. They allow describing the communication skeleton of a system. We consider a basic verification task for hierarchical MSCs, the matching problem via MSC templates. We characterize the complexity of checking properties which are expressible by and-or templates, resp. by LTL formulas. Both problems are shown to be PSPACE-complete.

Requirements engineering, the first phase of any software development project, is the Achilles' heel of the whole development process, as requirements documents are often inconsistent and incomplete. In industrial requirements documents, natural language is the main presentation means. This results in the fact that the requirements documents are imprecise, incomplete, and inconsistent. A viable way to detect inconsistencies and omissions in documents is to extract system models from them. In our previous work we developed approaches translating textual scenarios to message sequence charts (MSCs) and textual descriptions of automata to automata themselves. It turned out that these approaches are highly sensitive to proper definition of terms (communicating objects for MSCs, states for automata). The goal of the presented paper is a systematic comparison of different term extraction heuristics, as a preliminary stage of MSC or automata extraction. The extracted terms were declared to communicating objects (in the case of MSCs) or to states (in the case of automata). The heuristics were compared on the basis of correctness of resulting MSCs and automata. We came to the conclusion that named entity recognition is the best performing technique for term extraction from requirements documents.

Message Sequence Charts (MSCs) form a popular language in which scenariobased specifications and models can be written. There has been significant interest in automating aspects of testing from MSCs. This paper concerns the Oracle Problem, in which we have an observation made in testing and wish to know whether this is consistent with the specification. We assume that there is an MSC specification and consider the case where we have entirely independent local testers (local observability) and where the observations of the local testers are logged and brought together (tester observability). It transpires that under local observability the Oracle Problem can be solved in low-order polynomial time if we use sequencing, loops and choices but becomes NP-complete if we also allow parallel components; if we place a bound on the number of parallel components then it again can be solved in polynomial time. For tester observability, the problem is NP-complete when we have either loops or choices. However, it can be solved in low-order polynomial time if we have only one loop, no choices, and no parallel components. If we allow parallel components then the Oracle Problem is NP-complete for tester observability even if we restrict to the case where there are at most two processes.

Message Sequence Chart (MSC) is a graphical trace language for describing the communication behaviour of distributed systems. In order to build a Petri Net model of a complex system, this paper introduces a strategy to build a Petri Net model by using MSC. The algorithm of translating the MSC model to Petri Net model is also given in this paper. We can get the Petri Net model and improve it by translating the model of MSC. By analyzing the Petri Net model, it is proved to be safe and reliable.