An optimal algorithm for river routing with crosstalk constraints

As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with tbe objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising.

Traditional restrictions on river routing confine the connecting wires to the channel between the terminal rows. In [3] these restrictions were somewhat relaxed, thereby permitting a limited type of routing outside of the channel. In this paper we consider a further relaxation of the traditional constraints and consider a new class of “generalized” river routings. We show that this new class contains routings that are significantly more compact than those previously considered. In addition, we give a fast polynomial time algorithm for producing optimal routings in this new class. The running time of this algorithm is the best possible and is identical to the time required to produce optimal river routings under the traditional model.KeywordsChannel WidthOptimal RoutingMinimum SeparationSeparation AlgorithmGreedy FashionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The single-layer rectilinear river routing model with no restriction on the number of jogs per wire is considered. In particular, the author studies the model in which there is a fixed constant upper bound J on the number of jogs each wire can have. The author proposes an optimal O(n) time algorithm for the feasibility problem. This leads to an O(n log n) time algorithm for the minimum separation problem. Both algorithms take O(n) space are quite practical. This is a significant improvement over T.C. Tuan and S.L. Hakimi's (1987) minimum separation algorithm, which is designed for J=2 and takes O(n/sup 3/) time and O(n/sup 2/) space. >

We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that have linear-time sequential solutions rather than limiting attention to the “river-routing” context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lg N) time on a CREW PRAM or O(lg N/lg lg N) time on a CRCW PRAM, both with optimal work (processor-time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor bounds as long as only one side of the channel contains single-sided nets. For the optimal offset problem with single-sided nets on one side of the channel, we obtain time O(lg N lg lg N) on a CREW PRAM or O(lg N) time on a CRCW PRAM with O(N lg lg N) work. Not only does this improve on previous results for river routing, but we can obtain an even better time of O((lg lg N)2) on the CRCW PRAM in the river routing context.KeywordsParallel AlgorithmMinimum SeparationChannel BoundaryConvex CornerEfficient Parallel AlgorithmThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents a novel algorithm for crosspoint assignment (CPA) that takes into consideration crosstalk noise and shielding effects in deep sub-micron design. We introduce an alternative constraint which is imposed on a sensitive net-pair to detach one from the other or to put another insensitive net between them for shielding. We provide two algorithms: one is based on an ILP, which outputs an exact optimum solution. The other is a fast heuristics whose time complexity is O(n/sup 2/ log n), where n is the number of pins. In experiments, we tested these algorithms for industrial examples and demonstrated that our heuristics ran quickly and attained near optimum solutions.

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.

Channel routing and crosstalk minimization are important issues while we talk about high-performance circuits for VLSI physical design automation. Interconnection among the net terminals satisfying constraints in an intelligent way is a necessity to realize a circuit in a minimum possible area, as this is a primary requirement to reduce cost as well as to increase yield. In this paper, along with area minimization, the performance of the computed circuits has also been enhanced by computing routing solutions with a specified amount of bottleneck crosstalk in two-layer channel routing. Usually, crosstalk is measured by the amount of overlapping of a pair of nets assigned to adjacent tracks. The crosstalk minimization problem in the reserved two-layer Manhattan channel routing model is NP-hard. Thus, in this paper, heuristic algorithms have been devised to optimize bottleneck crosstalk in order to augment circuit performance in two-layer channel routing. Experimental results obtained are highly encouraging.

As fabrication technology advances, devices and interconnection wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Work on routing channels with reduced crosstalk is a very important area of current research [3],[10]. We know that the crosstalk minimization problem in the reserved two-layer Manhattan routing model is NP-complete, even for the channels without any vertical constraints. Since minimizing crosstalk is NP-complete, several polynomial time heuristic algorithms for reducing crosstalk have been developed [8],[9], [15]. All the ideas that are introduced as heuristics are basically sequential in nature. In this paper we have developed two efficient heuristics to compute reduced crosstalk routing solutions in a distributed computing environment. Our proposed heuristics are much better in computational complexity than the existing sequential versions of the algorithms developed in [9], [15].KeywordsBlank SpaceWire SegmentDistribute Computing EnvironmentParallel Random Access MachineTotal SpanThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Abstract. Global flood hazard maps can be used in the assessment of flood risk in a number of different applications, including (re)insurance and large scale flood preparedness. Such global hazard maps can be generated using large scale physically based models of rainfall-runoff and river routing, when used in conjunction with a number of post-processing methods. In this study, the European Centre for Medium Range Weather Forecasts (ECMWF) land surface model is coupled to ERA-Interim reanalysis meteorological forcing data, and resultant runoff is passed to a river routing algorithm which simulates floodplains and flood flow across the global land area. The global hazard map is based on a 30 yr (1979–2010) simulation period. A Gumbel distribution is fitted to the annual maxima flows to derive a number of flood return periods. The return periods are calculated initially for a 25 × 25 km grid, which is then reprojected onto a 1 × 1 km grid to derive maps of higher resolution and estimate flooded fractional area for the individual 25 × 25 km cells. Several global and regional maps of flood return periods ranging from 2 to 500 yr are presented. The results compare reasonably to a benchmark data set of global flood hazard. The developed methodology can be applied to other datasets on a global or regional scale.

Many problems that arise in general channel routing manifest themselves in simpler situations. We consider connecting a set of n terminals on a line to another set on a parallel line across a rectangular channel. We show that in any solution to the problem that (almost) minimizes the width of the channel (i.e. the distance between the lines the terminals reside on), (i) a net may require as many as O(vn) jogs, (ii) no net routed from top to bottom need ever turn upward in the middle. We also present an efficient algorithm to obtain minimal jogging in river routing, and provide necessary and sufficient conditions for conflict cycle resolution. These and other results are presented in the context of a general survey on routing from a combinatorial complexity point of view.

Through Silicon Via (TSV) technology is one of the most critical and enabling technologies for 3-D integration. Compared with conventional I/O structures, such as flip-chips, metal bumps, and wire-bonding, TSV technologies result in reduction of interconnect length, wire parasitics, propagation delay, and power consumption. Therefore, a compact model for a TSV is proposed based on electromagnetic simulations. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed wide-band TSV model are fitted to the simulated S-parameters up to 100 GHz with an error less than 5%.

Freezing ground, including permafrost and seasonally-frozen ground, is found in more than half of the Northern Hemisphere (NH). The changes in soil freezing/thawing, or the subsurface thermal conditions, are a local phenomenon, but can have large impacts on climate and life in cold regions. Permafrost (soil is at or below 0 C for more than two consecutive years), occupying about 20% of the exposed NH land, is an essential component in the hydro-eco-climate system in the Arctic. It defines and controls biogeochemical activities, types of dominant vegetation, hydrological states and conditions (e.g., water holding and storage capacity, river and channel routing, limnology) in the regions. However, the influences of local subsurface hydrological-thermal regime changes are not confined to the high-latitude regions. Multiple pathways, which are physical, ecological and/or biogeochemical, can transfer the subsurface changes to other regions, and affect the regional to global climate with different consequences. The carbon and nitrogen cycles are closely controlled by the presence of permafrost, degradation of which may cause an irreversible change in the cycle and accelerate the emission of greenhouse gases, such as carbon dioxide and methane. Some types of vegetation may not survive when the underlying permafrost degrades, leading to migration of other vegetation types. Consequent changes in albedo and evapotranspiration functionality will shift the budget of energy and water on large scales. Precipitation in the high-latitude, continental summer owes strongly to water recycling capability. Water availability in summer, therefore, may be altered following such changes in the surface and subsurface hydrological conditions.

A substrate that is designed to suppress parasitic modes while at the same time provides high-Q filtering capability is presented. High-density circuits require the integration of multiple functions in very limited space. More specifically, with the design of three-dimensional (3-D) circuits, parasitic effects caused by the excitation of surface waves result in a serious degradation of performance and impose limitations on circuit density and performance. Herein, an effort is presented to use advanced design concepts to enable embedded functionality within a substrate. The presented substrate geometries can easily be extended to 3-D to allow for the development of system-in-a-package which incorporates a high-Q filter bank to provide effective frequency selectivity. To demonstrate this concept, resonators and filters in LTCC are designed, fabricated and measured. Resonators in LTCC with unloaded Q up to 428 were measured. A narrow-band 2-pole filter is realized to show that a function of a relatively high-Q can be incorporated into the packaging. The 2.28% filter has an insertion loss of 1.7 dB due to the low loss nature of the design. Simulation and measurement of the structures are presented with good agreement achieved.

At the integration scale of System-On-Chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC designs., Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate level netlist and is formulated as a wire retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results showed the benefits and effectiveness of our approach.

Ceramic formulations set in an organic binder are currently being cast in thin paper-like sheets. These sheets may be punched, screened with metal pastes, and laminated to form a composite of metal and ceramic particles held together by an organic medium. By slowly burning off the organic binder and then sintering the ceramic and metal together, a substrate with many layers of interconnecting wiring may be obtained. The coincident sintering of the ceramic and metal phases presents compatibility constraints. Temperature considerations with respect to shrinkage and coefficient of expansion match between the ceramic and metal phases as well as solid/solid and solid/ambient interactions are important constraints in the fabrication of these composites. High conductivity metals (e.g., Ag, Cu) are generally not available for co-firing because sintering temperatures of important ceramic formulations are higher than the melting points of these metals. This constraint has been minimized through the use of capillary infiltration of molten metals into the ceramic structure. Consequently, it is now possible for multilayer ceramic structures to provide the interconnection wiring densities and conductivities necessary to respond to the needs of greater circuit densities of integrated circuit chips. Material selections are reviewed on the basis of electrical properties, ambient interactions, stresses due to sintering shrinkage, and thermal coefficient of expansion. Certain problems, tradeoffs, and procedures used in the fabrication of a multilayer substrate with Cu-filtrated lines are discussed.