Multifunctional substrates for high-frequency applications

At small electric devices, such as in particular medical devices, as e.g. hearing devices, very small electric coils (1) are used. Especially with hearing devices e.g. so-called t-coils are used. Those t-coils are considered and arranged at hearing devices as inductivities with parasitic effects. Due to the very limited space, it is proposed that at very small coils, which are used within the mentioned electric or electronic small devices, the connections of the coil (5, 7) are interlinked directly at the coil (1) over a component (9), an assembly group and/or a circuit. The connections of the coil (5, 7) are arranged on one or more screens or small panels which are firmly arranged on or at the coil comprising so-called pads (6, 8), which connections are interlinked with the use of a capacitor or condenser (9) and onto which pads external connections (11, 13) are directed for the external connecting of the coil.

A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

In this paper we present the possibility of shaping the reflectivity characteristics of tunable hyperbolic metamaterials (THMMs). Using the example of voltage-sensitive graphene-based structures, we demonstrate the existence of spectral and spatial functionalities of edge and narrowband filters, controlled dynamically over a 3-5μm spectral range, that are important for both civilian and military applications. We also demonstrate that the adoption of apodization techniques in the THMM design leads to a reduction in the sidelobe's parasitic effect in edge filters, as well as providing the means to reshape the overall reflectivity characteristics, which not only unveiled the tunable angle aperture functionality but also significantly increased the potential for tailoring optical properties of THMM nanostructures in general.

The results of analytical and experimental studies to determine the design technology needs of high temperature rise (AT) combustors and to define candidate design concepts for meeting these needs are reviewed. These studies show that several unique design considerations and constraints apply, because a high proportion of the available airflow must be allocated to the combustion process at the high AT operating conditions. This airflow allocation is necessary to obtain efficient combustion and acceptable smoke emission levels at the high AT conditions. Important technology needs include design features to provide stable operation over very wide AT ranges and design features to minimize liner-cooling airflow requirements. Candidate design concept features for providing these needed high A J combustor capabilities are described. Included are advanced design concepts to provide combustion process staging capabilities, as well as advanced liner-cooling and structural design concepts. The current development status of these various advanced design concepts is also assessed.

In the era of deep-nanoscale transistors, 3D structure of a FinFET strengthens the self-heating effect (SHE) that intensifies aging degradation. However, unlike planar devices, heat in FinFETs can improve the circuit performance due to the temperature effect inversion (TEI). This work investigates the impact of bias temperature instability (BTI) on long-term circuit performance in the presence of TEI. To accurately evaluate the device delay, the proposed unified TEI and BTI model takes into consideration temperature variation extracted from power dissipation in the device. The experimental results are carried out through selected combinational benchmark circuits under temperature and frequency variations. Compared to other recent approaches, this proposed method provides highly optimistic results in which either performance degradation (up to 2.3%) or improvement (up to 10%) can be found. Further, the results reveal that performance degradation due to the integration of BTI and TEI tends to worsen at high temperature, yet weaken at high frequency.

With storage and computation happening at the same place, computing in resistive crossbars minimizes data movement and avoids the memory bottleneck issue. It leads to ultra-high energy efficiency for data-intensive applications. However, defects in crossbars severely affect computing accuracy. Existing solutions, including re-training with defects and redundant designs, but they have limitations in practical implementations. In this work, we introduce row shuffling and output compensation to mitigate defects without re-training or redundant resistive crossbars. We also analyzed the coupling effects of defects and circuit parasitics. Moreover, We study different combinations of methods to achieve the best trade-off between cost and performance. Our proposed methods could rescue up to 10% defects in ResNet-20 application without performance degradation.

This paper presents a novel approach for a free structure analog circuit design using Genetic Algorithms (GA). A major problem in a free structure circuit is its sensitivity calculations as a polynomial approximation for the design is not available. A further problem is the effect of parasitic elements on the resulting circuit's performance. In a single design stage, circuits are produced that satisfy a specific frequency response specifications using circuit structures that are unrestricted and with component values that are chosen from a set of preferred values including their parasitic effects. The sensitivity to component variations for the resulting designs is performed using a novel technique and is incorporated in the fitness evaluation function. The extra degrees of freedom resulting form unbounded circuit structures create a huge search space. The application chosen is a LC all pass ladder filter circuit design.

This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design.

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Gallium nitride technology is becoming more popular nowadays and has been widely used to further improve the performance of power converters. As one of the most accessible GaN devices, cascode GaN devices have several advantages. The cascode GaN device is easier to manufacture and the reliability is improved in the semiconductor aspects. However, the short circuit capability has not been deeply studied and the performance degradation after short circuit remains unknown. In this paper, short circuit (SC) tests under different conditions are carried out and the comparison with traditional GaN devices is presented. Finally, the performance degradation after SC test is presented.

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. In this paper, we consider river routing with crosstalk constraints. Given the positions of the pins in a single-layer routing channel and the maximum tolerable crosstalk between each pair of nets, we give a polynomial time algorithm to decide whether there is a feasible river routing solution and produce one with minimum crosstalk whenever the problem is feasible.

The additive manufacturing process of multimaterial extrusion offers performance advantages using functional materials including conductors while making accessible the third dimension in the design of electronics. In this work, we show that the additional geometrical freedom offered by this technique can be exploited for the design and realization of filters made of 3-D resonators that exhibit enhanced characteristics. The coupling properties of 3-D grounded square split ring resonators (SRRs) are initially explored. We demonstrate by simulations and experiments that SRRs with finite height display significantly stronger coupling compared to equivalent thin printed circuit structures. The observed trend can be exploited for designing filters with wider operational bandwidths for a given footprint, or miniaturized layouts and enhanced compatibility with fabrication limits for minimum feature size and spacing without performance degradation. This concept is demonstrated by presenting results of full-wave simulations for sample bandpass filters with identical footprint but formed by coupled 3-D square SRRs of different heights, showing that filters with taller resonators exhibit increasingly wider bandwidths. Two filter prototypes with center frequencies at 1.6 and 2.45 GHz are manufactured by multimaterial 3-D printing. The measured characteristics of these prototypes are found to be in good agreement with numerical simulations taking into account the effect of the lossier metallic and dielectric materials used in 3-D printing and confirm the predicted larger bandwidth of the filters made of 3-D SRRs with marginally higher insertion losses.

Remote Direct Memory Access (RDMA) technique allows the messaging service that directly access the memory on remote machines, which provides low CPU overhead, low latency, and high throughput network transmission. On the other hand, however, due to the limited cache space in RDMA NIC (RNIC), it is still challenging to achieve effective and fair resource sharing across different applications. To address this problem, we present a scalable RDMA as a service to manage resource and deliver fair scheduling to applications' requests. We study the thread contention and preemptive schedule issues at end-hosts, and report the corresponding performance degradation through experiments. Then, we introduce Avatar, a model to manage memory and Queue Pairs (QPs) resource for a large number of connections, which eliminates the lock contention and provides fair data scheduling for applications with different priorities. Finally, we implement Avatar and demonstrate that Avatar can support a thousand of connections, improve the fairness and reduce the requests completion time up to 50% in comparison with the native RDMA.

Because of the tight coupling between closely spaced 3-D elements, parasitic effects often degrade the overall performance of complex MEMS circuits. A single-pole-double-throw (SPDT) switch in CPW technology consisting of a T-junction with one series-resistive and one shunt-capacitive MEMS switches per arm has been fabricated and tested. Parasitic coupling is shown to significantly affect the isolation of the isolated arm. While full-wave EM simulators would lead to unaffordable computational efforts to master such phenomena, a simple yet accurate planar approach recently presented is employed to effectively model and predict the behaviour of both the whole SPDT and its components. Having identified the portions of the circuit responsible for the spurious coupling, the planar approach has been used to modify the geometry of the shunt MEMS so as to minimize the parasitics, yielding a significantly improved performance of the SPDT.