An optimum parallel architecture for high-speed real-time digital signal processing

Digital signal processing techniques and architectures have evolved rapidly in recent years. As a consequence, the range of potential applications has broadened extensively in both existing areas such as radar and sonar signal processing and in relatively new fields such as communications and industrial condition monitoring. This article reviews the development and principal application areas for digital signal processing. The main architectural approaches to DSP design are then described with reference to practical examples where appropriate. Particular attention is given to programmable architectures, dedicated components and to ASIC-based systems.

Summary form only given. In high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs), an important problem is how to assign a proper fit type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve heterogeneous assignment problem, i.e., how to assign a proper FU type to a DSP application such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained from the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove heterogeneous assignment problem is NP-complete and propose several algorithms to solve it. The experiments show that algorithm DFG-assign-repeat is the best that gives a reduction of 25.7% on total cost compared with the previous work.

A CMOS gate array architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate arrays.

The key technology of realizing synthetic aperture radar (SAR) imaging is real-time processing of echo signal and a lot of data memory. However, it is very difficult to finish the work of SAR imaging system with single DSP chip. In order to resolve those problems, the DSP parallel processing system was designed, ADSP2106x is a high-speed and real-time digital signal processor that was produced by AD Company. Using the Links port of ADSP2106x, the DSP parallel processing structure was devised. In the meantime, SAR imaging processing structure and the performance and characteristics of ADSP2106x were introduced, besides, the advantages and disadvantages of these methods were described. DSP parallel processing system can satisfy the real-time requirement of the SAR imaging signal processing and has widely applied expectation in radar, communication and image processing etc fields.

Due to the pandemic, the vast majority of courses taught in the second half of 2020 proceeded online. We discuss the conversion of a Real-time Digital Signal Processing (DSP) course with traditional in-person hands-on labs to a hybrid (in-person and online) setting. This senior-level undergraduate course is built around the development and testing of DSP software. In the online version of the course, students use a small microcontroller kit and a USB oscilloscope, and they work in online teams. We describe the lab projects and we highlight the mechanisms that enable the students to collaborate on labs. We provide early feedback from students from the first offering of the modified course, and conclude with a list of planned improvements.

The design, implementation, and evaluation of a real-time digital signal processing architecture to generate and process multifrequency signals for eddy currents testing is described in this paper. This architecture is implemented on a dedicated instrument whose processing core is a field-programmable gate array. Stimulus generation is achieved using direct digital synthesis with some important improvements to reduce spurious frequency components. An in-phase and in-quadrature demodulation scheme is implemented to estimate the real and imaginary parts of the probe output signal. A cascaded integrator comb decimator is used to lower the sampling frequency and then allow narrowband filtering with low resources. The proposed architecture is able to generate and process the stimulus and input data at 125 MSamples/s and to estimate the input data components at 1.25 MSamples/s rate for eddy-currents with multiple simultaneous testing frequencies between 2.5 kHz and 10 MHz. Experimental validation is performed using a set of synthetic defects and two stimulus with different spectral composition.

Ultrasonic inspection system for tubular products using real-time digital signal processing

Onboard millimeter-wave radar is one way to improve helicopter flight safety at low altitudes in difficult meteorological conditions. Low-altitude flight is associated with the risk of collision with low-visibility obstacles such as power lines. Since power lines have the property of polarization anisotropy, it is necessary to use radar polarimetry methods to increase the radar visibility of such obstacles for detection. This paper investigates the possibility of identifying low-visibility polarization-anisotropic objects, such as power lines, in polarimetric images obtained by onboard helicopter radars to warn the pilot about the danger of a collision with a low-visibility object. Consequently, the use of a polarimetric radar with a polarization modulation of the emitted signal, the two-channel polarization synchronous reception of reflected signals and Eigenvalue signal processing in real time was proposed, aiming to eliminate the dependence of reflected signals on the spatial orientation of power transmission line wires. Additionally, an optimal algorithm for adaptive polarization selection, obtained by the maximum likelihood method, was proposed to detect such objects against the background of the underlying surface. The effectiveness of the proposed algorithm was tested using computer modeling methods. Moreover, a W-band polarimetric radar system was designed for experimental studies of this concept. The developed radar system provides digital real-time signal processing and the reconstruction of composite polarimetric images. It displays information about the polarization characteristics of the objects in the scanned area and the results of their polarization selection. Therefore, the system informs the pilot about dangerous objects along the helicopter’s route. Radar experimental tests in actual environmental conditions have confirmed the proposed concept’s correctness and the proposed method and algorithm’s effectiveness.

Field programmable gate arrays (FPGAs) are attractive for a digital spectrometer due to its advantages of digital signal processing. However, how to improve the versatility of the spectrometer and increase the operating frequency of the digital shaper has gradually become a limitation that needs to be resolved in the FPGA-based spectrometer. A solution to improve the universality of the FPGA-based digital spectroscopy system is presented in this work, and the implementation of the real-time digital signal processing unit is improved to obtain a higher operating frequency, and then the optimal parameters of the digital trapezoidal shaper and the processing unit are also discussed through a series of experiments; finally, a FPGA-based digital spectrometer is developed. With the HPGe detector, the spectrometer achieves excellent energy resolution performance of 0.35% at 662 keV, 0.25% at 1173.2 keV, and 0.23% at 1332.5 keV.

High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.

In this paper, we study existing designs proposed for the FPGA implementation of an LMS adaptive filter. Excess use of multipliers and longer cycle periods are a few of the issues associated with the existing structures. Based on this study, we propose a design for an FPGA implementation of an LMS based adaptive filter using the Xilinx DSP48. The proposed architecture uses one set of multipliers for both filter output and weight-increment term computation. We have simulated the proposed design for a 12-tap adaptive filter in Xilinx system generator and implemented the filter using the Vivado tool set. Implementation results shows that the proposed architecture uses 3 DSP48 units compared to 36 DSP48 units for the existing architecture with the same filter of size 12, and our implementation supports a 75% higher clocking frequency than the existing design. Additionally, the proposed architecture consumes nearly 4.7 times less dynamic power than the existing architecture. Therefore, the proposed architecture is suitable for efficient FPGA realization of an LMS FIR adaptive filter for real-time digital signal processing applications.

Current mobile phone applications demand high performance from the DSP, and future generations are likely to require even greater throughput. However, it is important to balance these processing demands against the requirement of low power consumption for extended battery lifetime. A novel low‐power digital signal processor (DSP) architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses these requirements through a multi‐level power reduction strategy. A parallel architecture and configurable compressed instruction set meets the throughput requirements without excessive program memory bandwidth, while a large register file reduces the cost of data accesses. Sign‐magnitude representation is used for data, to reduce switching activity within the datapath. Asynchronous design gives fine‐grained activity control without the complexities of clock gating, and gives low electromagnetic interference. Finally, the operational model of the target application allows for a reduced interrupt structure, simplifying processor design by avoiding the need for exact exceptions.

Traveling wave (TW) based protection and fault localization requires high sampling frequency measurements (500 kHz - 1 MHz) and are non-compliant to the IEC 61869-9 measurement standards, which allows maximum sampling frequency of 96 kHz for DC application. This work proposes a novel low sampling frequency (50 kHz) TW based primary protection and real-time DC fault localization technique for multi terminal high voltage DC (MTDC) grid which is compliant with the aforementioned measurement standard. In the proposed MTDC protection scheme, a TW arrival time (TWAT) is estimated under low sampling frequency measurement using cascaded combination of modified mathematical morphology gradient (MMG), sobel operator and linear regression tool. Subsequently, the TWAT information at both DC link terminals is communicated via dedicated communication channel compliant to IEC-61850-9-2 standard. And if the TWAT difference between DC terminals is less than the TW propagation threshold for the protected DC line, then a DC trip signal is issued to the associated hybrid DC circuit breaker (HDCCB). For fast power system restoration, the same TWAT information is also used for real-time fault localization in the faulted DC line, which is also compliant with IEC 61869-9 measurement standards. Finally, the practical feasibility of the proposed algorithm is demonstrated through control hardware-in-loop testing with real-time digital simulation setup and TI TMS320F28379d digital signal processor card.

The baseband implementation in cellular base stations for the latest standards specification always presents one of the most exacting challenges in real-time digital signal processing. This paper examines a practical approach to multi-core DSP which addresses the limitations of other technologies that are used to solve the problem and how it not only readily scales up to large high-complexity basestations using the latest techniques in multiple access and multiple antenna systems but down to the lowest cost, high volume systems such as Femtocell.

1-Gb/s multimedia service upstream transmission in real-time digital signal processing (DSP)-based orthogonal frequency division multiplexing-passive optical network (OFDM-PON) is experimentally demonstrated with centralized light source (CLS) configuration in this paper. After transmitted over 25km standard single mode fiber (SSMF) with-16.5dBm optical power at receiver, the bit error rate (BER) is 9.5×10-11. The implementations of digital domain up-conversion and down-conversion based on field programmable gate array (FPGA) are introduced, which can reduce the cost of in-phase and quadrature (IQ) radio frequency mixers utilized at transmitter and receiver. A new structure of frequency synchronization unit (FSU) designed in FPGA is also proposed to cope with the frequency shifting at receiver.