An ultra-broadband, high resolution frequency synthesizer

This article discusses the current state and development trends of microwave frequency synthesizers for test-and-measurement instruments. The discussed trends are also applicable for other synthesizer types used as modules in more complex systems. Test-and-measurement synthesizer market is estimated at $300 with an annual growth rate about 3%.A modern trend for the development of frequency synthesizers is associated with low phase noise, low spurious and fast switching speed. Important parameters also include operating frequency range, frequency resolution, modulation capabilities as well as size and cost characteristics. The main architectures based on direct analog, direct digital and indirect synthesis are evaluated. As of today, traditional indirect phase-lock-loop (PLL) architectures still dominate. On the other hand, direct analog synthesis is the most advanced approach that demonstrates extremely fast switching speed and low phase noise. Nevertheless, future developments are associated with direct digital synthesis (DDS) due to the rapid progress in solid-state technologies. DDS are currently available as special integrated circuits (IC) or can be build using field-programmable logic arrays (FPGA) and high-frequency digital-to-analog converters (DAC). Parallel (multichannel) digital structures coupled with high-frequency DACs allow generating output signals at microwave frequencies. Further improvements are possible using two or more DACs in an interleaved data mode. Wider frequency coverage through several tens of gigahertz and lower spur characteristics are expected.The article notes that modern frequency synthesizers allow generating complex signals using vector IQ-modulation. The modulation bandwidth is constantly increases through hundreds of megahertz or even several gigahertz. Further advances in microwave frequency synthesizers are associated with new reference types such as sapphire-loaded cavity oscillators with combined frequency stabilization as well as optoelectronic methods.

An experimental platform was developed to investigate the effects of audible sound (20 Hz to 20 MHz) on plant growth promotion, which included a microcontroller-based embedded system for audible sound adjustment and analysis. The direct digital frequency synthesis (DDFS) method was used to generate various waveforms of sound in the platform. Soundproof glass and mufflers were used to reduce background noise. The developed system was tested on various plants, including hydroponic tomatoes, celery and mung bean. The testing results showed that the developed platform could produce pure tone and mixing audible sound with high stability and accuracy, make octave analysis of the sound under experimental environments, and the background noise in the testing chamber of the platform was lower than 55 dB(A) when the compression engine was working. The developed experimental platform has a great potential on facilitating scientific research on acoustic biology effects on plants and collecting real-time experimental data. Keywords: plant growth, background noise, acoustic biology effect, direct digital frequency synthesis, sound sensor DOI: 10.3965/j.ijabe.20150805.1556 Citation: Cai W M, Zhu S M, Wang N, He H N, Ying B H. Design of an experimental platform to investigate the effects of audible sounds on plant growth. Int J Agric & Biol Eng, 2015; 8(5): 162－169.

Phase to amplitude conversion is an essential part in the technique of direct digital frequency synthesis. A novel theory of phase to amplitude conversion named curve approximation is proposed in this paper to solve the existing problems of present digital frequency synthesizers. It has more advantages over traditional phase to amplitude conversion methods, such as simple hardware circuit, fast conversion speed, low loss and high precision. A mathematical function approximating normalized waveforms is presented in the paper and then is corrected by a small ROM lookup table containing the difference between normalized waveform and curve approximation. It can be seen from MATLAB simulation that the given curve is essentially coincident with the normalized waveform. Frequency synthesizer based on DSP and MCU verifies the feasibility of curve approximation in direct digital frequency synthesis. Experimental result shows that this method has excellent performance.

In this paper, a triple-controlled direct digital synthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHz frequency synthesis is presented. The architecture has the merits of low spurs, a fast switching speed and high frequency resolution. It corrects the output of DDS and changes the division ratios of two variable frequency dividers in PLL to avoid high level spurs falling in the loop bandwidth of PLL. The additional DAC output is added to the output of the loop filter to drive the VCO. It provides the PLL with a fast switching speed. Experiment and measurement results showed that this type of frequency synthesizer architecture has better performance than conventional PLL and can be used in most applications of frequency synthesis.

Various modulation techniques are usually utilized to enhance the radar performance, or to add more capabilities to the radar that otherwise would not have been possible. Digital generation methods of frequency modulated continuous wave signals include direct waveform synthesis and frequency synthesis. The implementation of waveform generation and upconversion method are described in this paper with a simplified digital implementation technique using FPGAs (Field Programmable Gate Array). The design follows a systematic approach following steps of timing generation from external encoder, baseband modulated waveform generation, upconversion of the waveform to intermediate frequency, filtering and finally frequency synthesis using external DDS (Direct Digital Synthesizer). The design is also capable of generating BITE waveform for test checking in the system. Our design is capable of generation of waveform for stationary as well as non-stationary radars. For non-stationary radars, the waveform is so generated that the doppler effect due to the movement of the radar is compensated. The paper explains more on this. This work mainly focuses on the fact that the total design has been implemented on a single FPGA and the implementation solution utilizes the efficient FPGA resources so as to meet the timings in crucial applications. Moreover, the paper enhances the features of the design with simulation and real time results used to validate the design.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A frequency synthesizer based on SIP Technology with novel structure is presented in this paper, which combines the advantages of miniaturization and easy to maintain. The system is designed on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-MIX (Mixer), implemented in LTCC and Fuzz-Button. According to that, an excellent performance Ku-Band (14.6GHz~14.8GHz) frequency synthesizer SIP with low phase noise (<; -95dBc/Hz@1kHz) and low spurious in narrow band (<; -75dBc) is developed. Using this structure, the size of frequency synthesizer is reduced to 31.8x40.6x6mm.

The technique of direct waveform synthesis (DWS) is analyzed based on the technique of direct digital synthesis (DDS). The digital modulated waveforms are created by lookup tables (LUT) which contain waveform samples precomputed using the DWS technique. A novel DWS technique is proposed whose carrier frequency is programmable compared to the current one. Furthermore, the effect of memory versus computation is performed. The simulation results show that it is an efficient scheme to implement the software radio modulation for the DWS technique especially the novel technique of DWS with carrier frequency programmability.

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

This chapter provides a design of micro-broadband radar signal source based on direct digital frequency synthesis technology. This micro-broadband radar signal source is composed of baseband signal source and frequency multiplier chain. Direct Digital Synthesis (DDS) chip AD9858 was used in the baseband signal source. A FPGA chip was employed to load DDS control words to create 200MHz ± 50MHz baseband signal. Multiplier chain achieved up-conversion and frequency doubling of baseband signal, and output 1.5GHz + 400MHz broadband radar Linear Frequency Modulated (LFM) signal. Oscilloscope and spectrum analyzer measurements results showed that the quality of LFM signal met the design requirements.KeywordsExcitation SignalLinear Frequency ModulateBaseband SignalLinear Frequency Modulate SignalFPGA ChipThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Long Range(LoRa) Backscattering Communication (BC) not only has the advantages of low cost and low power consumption, but also has a long communication distance. However, the existing LoRa BC scheme is complex and can not be applied to actual engineering. For this purpose, a new LoRa BC method is proposed. A Direct Digital frequency Synthesis (DDS) technique is used to generate a square wave with a linear frequency variation as a LoRa scattering modulation signal. For the first time, the prototype of LoRa BC system based on MCU is demonstrated. Experimental results show that design can successfully realize backscatter communication at any position between the station and the receiver which are 208 meters apart, while being compatible with commodity LoRa chipset. In addition, the method is also applicable to an Application Specific Integrated Circuit (ASIC) design, which enables the LoRa backscattering IC to have higher robustness, lower cost, and lower power consumption.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

This paper describes a new architecture of a digital fractional frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method e.g. SigmaDelta fractional-N frequency synthesizers or direct digital synthesis. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration (or in-system programmable Large Scale Integration). On the other hand, this synthesizer has a disadvantage in low output frequency, but this can be overcome by using this synthesizer together with phase locked loop.

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth and settling time requirement. System analysis shows that this structure can meet the stringent requirement of DCS1800. This structure is designed with a 0.18 /spl mu/m CMOS process. Excluding of DDS, the synthesizer core dissipates 9.5mW from a 1.8V supply.