Direct digital frequency synthesizer based on curve approximation

Long Range(LoRa) Backscattering Communication (BC) not only has the advantages of low cost and low power consumption, but also has a long communication distance. However, the existing LoRa BC scheme is complex and can not be applied to actual engineering. For this purpose, a new LoRa BC method is proposed. A Direct Digital frequency Synthesis (DDS) technique is used to generate a square wave with a linear frequency variation as a LoRa scattering modulation signal. For the first time, the prototype of LoRa BC system based on MCU is demonstrated. Experimental results show that design can successfully realize backscatter communication at any position between the station and the receiver which are 208 meters apart, while being compatible with commodity LoRa chipset. In addition, the method is also applicable to an Application Specific Integrated Circuit (ASIC) design, which enables the LoRa backscattering IC to have higher robustness, lower cost, and lower power consumption.

An experimental platform was developed to investigate the effects of audible sound (20 Hz to 20 MHz) on plant growth promotion, which included a microcontroller-based embedded system for audible sound adjustment and analysis. The direct digital frequency synthesis (DDFS) method was used to generate various waveforms of sound in the platform. Soundproof glass and mufflers were used to reduce background noise. The developed system was tested on various plants, including hydroponic tomatoes, celery and mung bean. The testing results showed that the developed platform could produce pure tone and mixing audible sound with high stability and accuracy, make octave analysis of the sound under experimental environments, and the background noise in the testing chamber of the platform was lower than 55 dB(A) when the compression engine was working. The developed experimental platform has a great potential on facilitating scientific research on acoustic biology effects on plants and collecting real-time experimental data. Keywords: plant growth, background noise, acoustic biology effect, direct digital frequency synthesis, sound sensor DOI: 10.3965/j.ijabe.20150805.1556 Citation: Cai W M, Zhu S M, Wang N, He H N, Ying B H. Design of an experimental platform to investigate the effects of audible sounds on plant growth. Int J Agric & Biol Eng, 2015; 8(5): 162－169.

A ROM-less direct digital frequency synthesizer (DDFS) is implemented based on a new 8th-order polynomial approximation of a cosine function, where digital square circuits are used to realize the components of the polynomial. MATLAB tools are used to simulate the performance of the DDFS system, where the spurious free dynamic range (SFDR) is employed as the performance factor. For a DDFS with a superior quality, the higher the SFDR, the better the spectrum purity. To validate the performance of the DDFS, the Altera FPGA platform is used with Quartus II and ModelSim, where simulation results based on Verilog implementation are illustrated.

A quadrature direct digital frequency synthesizer (DDFS) was designed and implemented in a 1.2 µm CMOS process using two non-linear resistor string DACs. These DACs are used in place of the phase-to-amplitude ROM look-up tables and the linear DACs in a conventional quadrature DDFS to give a low power design. At 25 MHz clock frequency, the DDFS dissipates less than 4 mW at 3.3 V and has SFDR better than 55 dBc at low synthesized frequencies.

Direct digital frequency synthesis (DDS) as an indispensable key technology for modern communication systems, is widely used in digital communications, satellite communications, aerospace and high-speed instrumentation. In practical applications, DDS technology is usually required to generate different kinds of communication signals. In view of the fact that there is no related research on spurious signals when DDS technology generates communication signals, this paper based on a DDS model that can generate arbitrary symbol rate communication signals, analyzes spurious signals of the structure in detail. The conclusions of this paper can be used for the spur evaluation and parameter selection in DDS engineering applications. At the same time, this paper provides a theoretical basis for the low spurious design of DDS, and has certain reference value for DDS to generate communication signals.

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

This paper presents an ultra-high-speed direct digital frequency synthesizer (DDS) microwave monolithic integrated circuit (MMIC) implemented in 1μm GaAs HBT technology. The DDS has the capabilities of direct frequency modulations with 8-bit frequency resolutions. Utilizing a Double-Edge-Trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC based ROM-less architecture, this DDS MMIC can maximize the utilization ratio of GaAs HBT's high-speed potential. With an external clock output frequency of 5GHz, the DDS can output sine signal of up to 5GHz frequency giving an average Spurious Free Dynamic Range (SFDR) of 23.24dBc through the first Nyquist band. The DDS MMIC consumes 2.4W of DC power from a single -4.6V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 × 2.0mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Direct Digital Frequency Synthesizer (DDFS) has long been perceived as a predominant solution for producing precise, variable frequency signals having very low distortion. The paper presents an epigrammatic and a comparative study of direct digital frequency synthesizers architectures. The direct digital frequency synthesizer presented are compared on the basis of two architectures namely, the read only memory (ROM) or look up table based architecture and the other co-ordinate rotation based digital computer that eliminates the usage of the large ROM based look up table. These architectures are compared in terms of the power utilization, SFDR, etc. A mixed signal ASIC designing approach is followed for the implementation approach.

In order to test the working state of adaptive optics system, it is necessary to design an online sweep-frequency circuit module to test the frequency response of the adaptive system. Sweep-frequency signal generator based on Direct Digital frequency Synthesis (DDS) is one of the core components. But the classic DDS technology also has some drawbacks: the truncation error of phase, the truncation error of magnitude (caused by memory FWL) and high occupancy of ROM. These are also the optimization directions in this paper. This paper presents a FPGA-based DDS sweep-frequency signal generator suitable in adaptive optics. It has a low occupancy rate with ROM. And in the case of low-ROM, the paper reduces the noise generated by the truncation error of phase and the truncation error of magnitude of DDS sweepfrequency signal generator by method of linear interpolation. The results show that, when the reference frequency is 100 MHz, the frequency resolution can be as low as 0.025 Hz. It only takes up 0.5 KB ROM with the ROM compression ratio of 64:1 in the optimized scheme in the paper and has higher precision due to the method of linear interpolation than the unoptimized scheme, which can meet the engineering needs. Compared with other schemes, the scheme in the paper improves signal accuracy in the case of reducing the truncation error of phase, the truncation error of magnitude and the occupancy rate with ROM, but only adds a multiplication and division circuit, which is a practical solution.

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

This paper introduces a novel Direct Digital Frequency Synthesizer (DDFS) based on Complementary Dual-Phase Latch-Based digital design. Compared to conventional DDFS using Flip-Flop as synchronizing element, the proposed approach allows to double the sampling data rate while enhancing the clock skew tolerance and system latency. The design features a 24 bits pipelined Phase Accumulator (PA) and a 14×10 bits Phase to Amplitude Converter (PAC). The Phase to Amplitude Converter module is compressed using Quarter Wave Symmetry technique and is entirely made up of combinational logic inserted into 12 Complementary Dual-Phase Latch-Based pipeline stages. The logic is represented in the form of Sum of Product (SoP) terms obtained from a 14×10 bits sinusoidal Look-Up-Table. The proposed DDFS is designed and simulated based on TSMC 65nm CMOS standard-cell technology. A maximum data sampling rate of 6.8 GS/s and 0.022 W/ GS/s Power Efficiency (PE) is expected.

This brief presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> integrated over a 100MHz bandwidth with 28.25Hz resolution while consuming less than 3mW at sampling clock 3.12GHz. The proposed DDFS is fabricated in a 0.9V TSMC 7nm CMOS process and occupies a core area of only 0.014mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Vitesse wins InP from DARPA

In this paper, we analyze the design and the possible optimization methods of the direct digital frequency synthesizer (DDFS) based on quadratic approximation. The goal is to design a DDFS with reduced hardware cost and very high spectral purity. For the DDFS based on quadratic approximation, there is a trade-off between the size of the memory and the approximation logic. We show that by exploring this trade-off, it is possible to design a DDFS which requires less hardware and features higher spectral purity than the previously presented solutions. By using the proposed design method, a DDFS that generates 16-bit sinusoidal waves with a spurious free dynamic range of 132 dBc (126 dBc if the phase is truncated) was designed.