ANALYSIS AND DESIGN OF FEEDBACK CONTROL SYSTEMS WITH TRACKING ERRORS SQUARE

Costas loops are invariably designed in conjunction with an automatic gain control (AGC) loop for stabilizing performance. In such systems an inherent coupling between the AGC and Costas loops develops, complicating the standard phase referencing analysis. This coupling is further emphasized if the gain control amplifier introduces an AM/PM conversion, which causes power variations to enter the Costas loop as phase variations. In this paper the coupling effect between AGC and Costas loops is developed, leading to a pair of joint, interconnected dynamical tracking loops. Some degree of solution is attainable by assuming a first order AGC loop, and resorting to quasi-stationary analysis for evaluating the phase referencing generation. Results with and without AM/PM are presented, and illustrate how an improper AGC may in fact degrade the phase referencing from the expected performance.

This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang-bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves <; 290 fs integrated rms jitter and <;- 72.89 dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of -245 dB.

An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 ¿m CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.

In read channels in magnetic recording systems, a finite impulse response (FIR) filter is often used as an equalizer, and the filter coefficients are adapted via a least mean squares (LMS) algorithm. This equalizer adaptation loop can interfere with the timing recovery (TR) loop and the automatic gain control (AGC) loop that are also present in such channels. In a previous paper by L. Du et al., a linear constraint is proposed for the LMS loop so that it is decoupled from the TR and the AGC loops. In this paper, we generalize that constraint, and propose a new constraint that offers the advantage of easier implementation.

In this literature, a data pre-processing circuit designs and analyses for an infrared image seeker of a subsonic cruise missile are proposed.The flight speed of the missile is 250m/s.Therefore, automatic contrast control and automatic brightness control are usually needed to keep wanted contrast and brightness for best image properties in target recognition and tracking; especially for the missile at the terminal approaching phase to prevent signal saturation.Signal saturation implies target lost.The major parameters of imaging systems for contrast and brightness controls include average, maximum and minimum of gray level of the whole picture in the sampling interval.Therefore, the overall system is a complicated nonlinear sampled-data control system.It is difficult to describe, analyze and design the system.In this literature, the overall system is first decomposed into two linearized sampled-data control systems to get needed loop compensations, and verified by a special range-dependent testing signal to the overall system secondly.The controlled system is further verified by a thermal plate and real flight testing.Testing results give the proposed method can provide effective way to analyze and design the considered system. Minimal (MIN) Brightness Maximal (MAX) BrightnessD/A APC Control Signal(60Hz) CCD Focal Plane Array Pre-Processing Circuits AGC Control Circuit APC Control Circuit Amplifier Circuit A/D D/A AGC Control Signal(60Hz) Addressing for Desired Cell (256x256x60Hz) Micro-Processor MAX/ MIN/ AVG Digital Filters for APC Digital Filters for AGC

An 80 Mbit/s amplifier has been developed for the optical receiver of the CMS tracker control link. Four channels of the circuit have been integrated in a 0.25 ∝ m commercial CMOS process using radiation tolerant layout practices to achieve the required radiation tolerance. An Automatic Gain Control (AGC) loop allows for detection of wide dynamic range input signals (10 ∝ A to 500 ∝ A photocurrent) with minimum noise, compatible with the maximum expected radiationinduced drop in quantum efficiency of the PIN photodiode. A second feedback loop compensate a photodiode leakage current up to 100 ∝ A.

This article presents a low-power two-stage feedforward self-interference cancellation (SIC) receiver designed for frequency-division duplex (FDD) applications. By relocating the feedforward SIC path to the second stage, the additional noise contributed from the SIC path can be reduced by the first-stage amplifier. Moreover, an automatic gain control (AGC) loop continuously monitors the amplitude difference between the two paths and adjusts the programmable-gain amplifier (PGA) gain until the residual interference is minimized. Measurement results show a maximum conversion gain (CG) of 46 dB and a minimum noise figure (NF) of 4 dB across the 6.4–7.1-GHz band. The SIC technique achieves up to 32-dB interference suppression while maintaining receiver performance under TX interference up to −20 dBm. The prototype consumes 24.1 mW and occupies 2.58×1.35 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed receiver demonstrates competitive power efficiency, SIC performance, and robustness for emerging FDD wireless applications.

An up-down counter, multiplier, digital-to-analog (D/A) converter, and high-speed comparators are employed to achieve an automatic gain control (AGC) circuit, which corrects the pair of characteristic roots of the overall system automatically to the imaginary axis of the complex frequency plane. A negative feedback technique with digital hardware is applied on the loop gain control. No lowpass filter is needed to detect the oscillation amplitude. Thus, this technique is suitable for sinusoidal oscillators with a wide oscillation frequency range. Wien-bridge and phase-shift oscillators with an oscillation frequency range from 17 Hz to 1 MHz are tested with the proposed AGC circuit. The total harmonic distortions of the Wien-bridge sinusoidal oscillator with the proposed AGC circuit are verified to be very small. An application to a variable-frequency sinusoidal oscillator is also described. The experimental results demonstrate the static characteristics and dynamic responses of the overall system.

Wireless LAN (WLAN) operating in the 5-6 GHz range, become commercially viable only, if they can be produced at low cost. Consequently, tight integration of the physical layer, consisting of the radio front-end and the digital signal processing part, is a must. Especially with respect to mixed-signal feedback loops, with automatic gain control as a recurring example, existing tools have major difficulties in offering efficient ways of modeling and simulation. We present a modeling approach where the complexity of the analog behavioral model has been reduced to the minimum required by the digital receiver, namely its steady-state responses and a ýworst-caseý time delay. Moreover, we show how this mixed-signal receiver model can be used in an end-to-end communication link simulation to provide the designer insight into statistical information such as transient delays and gain tolerances. For this model, we set up a co-simulation of two existing in-house tools, one for the analog part, the other for the digital system part.

Wireless LAN (WLAN) operating in the 5-6 GHz range, become commercially viable only, if they can be produced at low cost. Consequently, tight integration of the physical layer, consisting of the radio front-end and the digital signal processing part, is a must. Especially with respect to mixed-signal feedback loops, with automatic gain control as a recurring example, existing tools have major difficulties in offering efficient ways of modeling and simulation. We present a modeling approach where the complexity of the analog behavioral model has been reduced to the minimum required by the digital receiver, namely its steady-state responses and a ýworst-caseý time delay. Moreover, we show how this mixed-signal receiver model can be used in an end-to-end communication link simulation to provide the designer insight into statistical information such as transient delays and gain tolerances. For this model, we set up a co-simulation of two existing in-house tools, one for the analog part, the other for the digital system part.

Pulse oximeters are ubiquitous in modern medicine to noninvasively measure the percentage of oxygenated hemoglobin in a patient's blood by comparing the transmission characteristics of red and infrared light-emitting diode light through the patient's finger with a photoreceptor. We present an analog single-chip pulse oximeter with 4.8-mW total power dissipation, which is an order of magnitude below our measurements on commercial implementations. The majority of this power reduction is due to the use of a novel logarithmic transimpedance amplifier with inherent contrast sensitivity, distributed amplification, unilateralization, and automatic loop gain control. The transimpedance amplifier, together with a photodiode current source, form a high-performance photoreceptor with characteristics similar to those found in nature, which allows LED power to be reduced. Therefore, our oximeter is well suited for portable medical applications, such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing. Furthermore, our design obviates the need for an A-to-D and digital signal processor and leads to a small single-chip solution. We outline how extensions of our work could lead to submilliwatt oximeters.

An all digital architecture was presented to realize the logarithm modeled automatic gain control(AGC) loop based on field programmable gates array(FPGA) platform.The architecture is mainly made up of four modules,including envelope detector,coordinator rotation digital computer(CORDIC) based iterative realization of effective hyperbolic function,infinite impulse response(IIR) based loop filter,and reconfigurable control logic generator.Envelope detector can meet the filter performance requirement only with finite impulse response(FIR) filter of low order.Symmetric coefficient based transposed architecture reduces the number of multipliers in filter to the half.By approximation to analog integrator and suitable process,IIR based filter can simplify the architecture of digital integrator.The logarithm convertor is easy to be realized by CORDIC based iterative hyperbolic function processor.The architecture can also output with random precision,and realize the compromise of circuit resources and speed,which overcomes the high demand for random access memory(RAM) in traditional algorithms.With fully parallel pipeline architecture,the maximum working clock can achieve 206 MHz.Finally,the realization results based on the FPGA processor and the hardware simulation were given.Experimental results were consistent well with the theoretical analysis.

A dual-channel fully integrated RF receiver is designed and implemented for next generation Global Navigation Satellite Systems (GNSS) in a 0.18μmCMOS process. Its two independent channels are capable of receiving 2MHz, 4MHz or 20MHz bandwidth signals around 1.2GHz and 1.57GHz, for GPS, Galileo, and Compass systems. Gain controls along with an all-digital automatic gain control (AGC) loop are implemented in each channel to improve the noise and anti-interference performance of the receiver. While drawing 25mA current per channel from a 1.8V supply, this receiver achieves a total noise figure of 2.5dB/2.7dB and a maximum voltage gain of 115dB/112dB at 1.2GHz/1.57GHz, respectively, with a die area of 2.4×3mm2 including ESD and I/O pads.

This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive coupling between inputs of the op-amp. In presented amplifier modulators are placed outside capacitive feedback which improves noise and gain performance. Proper gain distribution between stages contributes to minimizing output noise and phase shift. Chopper ripple is of no concern because of low pass filters in phase-locked loop in signal processing circuit. Proposed circuit is designed in 0.18 CMOS technology. The chopper amplifier consumes 1.75 mA current. Input referred noise voltage at 15 kHz is 8.2 nV/√Hz, gain of the amplifier is 53 dB while the phase shift is 0.6°.

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMS, and the chip size is 10 mm x 10.1 mm which is fabricated using a 0.8 μm 2 metal CMOS technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32k (2k x 16 bit) RAM, and 240k (10kx24 bit) ROM. The die size is 8.7 mmx8.3 mm and the chip is fabricated using 0.8 μm CMOS technology.