Analysis and performance of computer instruction sets [Thesis

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

Reduced instruction set computer (RISC) processors are built on the philosophy of eliminating complex instructions and of limiting the instruction set to only simple operations, thereby emphasizing fast execution. This approach has been adopted in many modern processors. Extending the RISC concept even further, we propose mono instruction set computer (MISC) architecture, which constrains the number of instructions on a processor to a single instruction. Because a MISC processor contains only a single instruction, in order to execute a variety of instructions, MISC processors must be implemented onto a programmable architecture and its configuration must be done frequently. Existing FPGAs can not achieve a high-performance MISC processor due to their long reconfiguration time. Therefore, we have been developing an optically reconfigurable gate array (ORGA) that supports high-speed dynamic reconfiguration. The ORGA can realize an ideal platform for MISC processors. In this research, we designed MISC processors based on RISC-V processor using the high-level hardware description language FSL. The design has been implemented onto an FPGA. This paper presents the evaluated results.

Recent advances in different instruction set architectures (ISAs) and their implementations have revived the argument on the role of ISAs in the overall performance and energy efficiency of a processor. Many computer architects believe that with current compiler and microarchitecture developments, the choice of ISA is not a decisive matter anymore. On the other hand, some believe that ISAs can still play an important role in the overall performance and energy efficiency of a computer system. Our objective is to compare and contrast ISAs by finding the differences in performance and energy consumption across ISAs and the reasons behind those differences. Our work shows that ISAs affect the performance and energy efficiency of applications differently based on their inherent characteristics.

The single or one instruction set computer (OISC, pronounced, “whisk”) is the penultimate reduced instruction set computer (RISC)1. In OISC, the instruction set consists of one instruction, and then by the orthogonality of the instruction along with composition, a complete set of operations is synthesized. This approach is completely opposed to a complex instruction set computer (CISC), which incorporates many complex instructions as microprograms within the processor.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Chapter 11 - The ARM Architecture

We describe a novel architectural framework that allows software applications written for a given Complex Instruction Set Computer (CISC) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. The framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). High execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. Issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. Relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture.The proposed framework offers a path for moving from complex instruction set computers (CISCs) to newer architectures, such as reduced instruction set computers (RISCs), superscalars, or very long instruction word (VLIW) machines, while protecting the extensive economic investment represented by existing software. To illustrate our approach, we show how system code written (and compiled) for the IBM System/390 can yield fine-grain parallelism, as it is targeted for execution by a VLIW machine, with encouraging performance results.

In this work, we present an exploration platform for microcoded RISC-V cores leveraging the One Instruction Set Computer (OISC) principle. Following the industry-proven virtual prototyping approach, we have realized our exploration platform by implementing an extensible and configurable Instruction Set Simulator (ISS). The developed ORISCV-ISS combines the advanced ecosystem of RISC-V with the ultimate minimalism of OISCs. ORISCV-ISS serves as development platform for both, hardware architecture and microcode procedures, and provides the basis for early design space exploration. Using ORISCV-ISS, we developed SUBLEQ microcode that is fully RISC-V compliant and ready to be run on real hardware. We evaluate how multiple hardware configurations and OISC extensions affect the performance, providing key information to balance between area savings and system performance.

12 - The next generations

The evolution of computer architecture has given rise to two main approaches: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These architectures differ significantly in terms of instruction design, efficiency, and performance. This study aims to analyze the performance and efficiency of RISC and CISC in the context of computer architecture organization. The methodology includes a literature review, comparative analysis, and performance evaluation based on parameters such as processing speed, power consumption, and design complexity. The results indicate that RISC tends to be more efficient in terms of power consumption and execution speed for simple instructions, while CISC excels in handling complex instructions with fewer lines of code. The findings of this study can serve as a reference for the development of modern computer architectures that balance performance and efficiency.

Computer languages design is a fundamental subject in Computer Science and instruction sets are not an exception. Considering concurrency, and particularly superscalar processing, an important fact is to identify those characteristics of the instruction set architecture that may cause extra code coupling. Because of its current extended use, the x86 instruction set was chosen for analysis. We present a study of the use distribution of architectonic registers, including implicit usage, taken from execution traces of a test bench. Then we identify as potential coupling sources the implicit and dedicated use of certain registers, condition codes utilization and some mechanisms of effective memory address computation.

Computer systems courses, including computer organization, architecture, operating system, compiler, and other relevant courses, play an important role in cultivating students' computational thinking, especially the ability of viewing hardware and software in a computer system as a whole. In order to help learners to better understand principles and concepts taught in lectures of aforementioned courses, some visionary instructors have started to design lab projects for their courses with real-world instruction set architectures (ISAs), such as MIPS, ARM and x86, or even request students to conduct projects on these ISAs-based hardware platforms. Meanwhile, with the overwhelming trend towards AI, IoT and heterogeneous computing, RISC-V, an open and free ISA, has emerged and recently attracted a lot of attention from both academia and industry. Compared with proprietary ISAs, RISC-V is more simple, affordable, extensible and compatible. Given this context, several arising questions can be examined and discussed in this BoF session. For example, 1) whether the computer systems courses should integrate RISC-V, 2) do we need minor (evolutionary) or major (revolutionary) curriculum changes with the involvement of RISC-V for each course or the entire CS curriculum, 3) how to help the majority of students accommodate to these changes, 4) what kind of new course materials should be provided to instructors, TAs and students, 5) whether it's possible for some senior students to tape-out their own RISC-V chip designs and finally produce a cornucopia of workable computing systems with this revolutionary and open curriculum.

E-Learning automation is a set of computer instructions used to solve the difficulties of effective E-Learning systems management. And based on the merits of natural language processing techniques, E-Learning automation has already achieved great progress, such as automatic E-Learning online quizzes creation and students’ questions answering. This research mainly focuses on finding a powerful method for E-Learning contents creation to solve the problem of difficulties in E-Learning system management. This research can be mainly divided into four steps: Firstly, automatically summarize relevant texts to get straightaway texts from the source version. Secondly, detect keywords from generated summaries. Then, delete the detected keywords from summaries. Finally, rearrange outputs from previous steps to generate online questions and learning materials.

Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$+$$\\end{document} lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in the Sail language, and arbitrary axiomatic relaxed-memory concurrency models, in the Cat language. It is based on a generic symbolic engine for Sail ISA specifications. We equip the tool with a web interface to make it widely accessible, and illustrate and evaluate it for Armv8-A and RISC-V. The symbolic execution engine is valuable also for other verification tasks: it has been used in automated ISA test generation for the Arm Morello prototype architecture, extending Armv8-A with CHERI capabilities, and for Iris program-logic reasoning about binary code above the Armv8-A and RISC-V ISA specifications. By using full-scale and authoritative ISA semantics, Isla lets one evaluate litmus tests using arbitrary user instructions with high confidence. Moreover, because these ISA specifications give detailed and validated definitions of the sequential aspects of systems functionality, as used by hypervisors and operating systems, e.g. instruction fetch, exceptions, and address translation, our tool provides a basis for developing concurrency semantics for these. We demonstrate this for the Armv8-A instruction-fetch and virtual-memory models and examples of Simner et al.

This work presents the proof of concept implementation for the first hardware-based design of Moving Target Defense over IPv6 (MT6D) in full Register Transfer Level (RTL) logic, with future sights on an embedded Application-Specified Integrated Circuit (ASIC) implementation. Contributions are an IEEE 802.3 Ethernet stream-based in-line network packet processor with a specialized Complex Instruction Set Computer (CISC) instruction set architecture, RTL-based Network Time Protocol v4 synchronization, and a modular crypto engine. Traditional static network addressing allows attackers the incredible advantage of taking time to plan and execute attacks against a network. To counter, MT6D provides a network host obfuscation technique that offers network-based keyed access to specific hosts without altering existing network infrastructure and is an excellent technique for protecting the Internet of Things, IPv6 over Low Power Wireless Personal Area Networks, and high value globally routable IPv6 interfaces. This is done by crypto-graphically altering IPv6 network addresses every few seconds in a synchronous manner at all endpoints. A border gateway device can be used to intercept select packets to unobtrusively perform this action. Software driven implementations have posed many challenges, namely, constant code maintenance to remain compliant with all library and kernel dependencies, the need for a host computing platform, and less than optimal throughput. This work seeks to overcome these challenges in a lightweight system to be developed for practical wide deployment.