A Study of Performance and Power Consumption Differences Among Different ISAs

The energy efficiency of space heaters is rated by Annual Fuel Utilization Efficiency (AFUE) governed by the Department of Energy in the United States which is a simple ratio of usable heat and fuel usage of a single heating device. It doesn't consider the overall performance of the heating system including not only the heating devices but also the characteristics of the building in different applications. The current AFUE method calculates only the energy efficiency which is thermodynamics first law efficiency. In this research, the systematic efficiency of a heating system rather than simple device efficiency has been defined and investigated. The systematic efficiency considers the overall efficiency of the whole heating system and it varies in the different applications even though with the same heating device. So it represents the performance of the system more precisely. Analytical models have been built to calculate both the systematic energy efficiency and exergy efficiency, and to evaluate the systematic energy and exergy efficiency of heating systems for direct fired and indirect fired heaters. Efficiency performances of the systems with these two types of heaters are compared. Sensitivities of input parameters for systematic energy efficiency are studied to show the impact towards systematic energy efficiency. Indoor carbon dioxide concentration level of direct fired heating system is also studied. In a case study, results show that systematic energy efficiency of indirect fired heating system is always constant at heater device efficiency which is 80\% while systematic energy efficiency of direct fired heating system varies from 40%-92% under different condition (heat loss coefficient, ambient temperature and air change requirement), indicating that simple device efficiency is not capable to evaluate the overall performance of heating system. New efficiency method such as systematic energy efficiency used in this research is needed to better describe the performance of the heating system. Results of indoor carbon dioxide level of direct fired heating system, from 1000 to 4500 PPM under different conditions, show that indoor air quality needs to be considered while using direct fired heating.

Computer systems courses, including computer organization, architecture, operating system, compiler, and other relevant courses, play an important role in cultivating students' computational thinking, especially the ability of viewing hardware and software in a computer system as a whole. In order to help learners to better understand principles and concepts taught in lectures of aforementioned courses, some visionary instructors have started to design lab projects for their courses with real-world instruction set architectures (ISAs), such as MIPS, ARM and x86, or even request students to conduct projects on these ISAs-based hardware platforms. Meanwhile, with the overwhelming trend towards AI, IoT and heterogeneous computing, RISC-V, an open and free ISA, has emerged and recently attracted a lot of attention from both academia and industry. Compared with proprietary ISAs, RISC-V is more simple, affordable, extensible and compatible. Given this context, several arising questions can be examined and discussed in this BoF session. For example, 1) whether the computer systems courses should integrate RISC-V, 2) do we need minor (evolutionary) or major (revolutionary) curriculum changes with the involvement of RISC-V for each course or the entire CS curriculum, 3) how to help the majority of students accommodate to these changes, 4) what kind of new course materials should be provided to instructors, TAs and students, 5) whether it's possible for some senior students to tape-out their own RISC-V chip designs and finally produce a cornucopia of workable computing systems with this revolutionary and open curriculum.

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

In this paper we concentrate on the effect of instruction set architecture on the performance potential of a computer system. These issues are key in considerations of what instruction set is most appropriate for the support of high level languages on general purpose machines. Two possible approaches are so called complex instruction sets, such as those of the VAX and IAPX 432, and the “reduced” instruction set of the RISC I [2] microcomputer, which is expected to have performance similar to that of a VAX 11-780. We propose a method of instruction set interpretation that takes advantage of the architectural features of complex instruction sets. These methods have been simulated executing real programs and in the case of the VAX instruction set have resulted in a typical improvement of a factor of two, assuming the same cycle time as the VAX 11-780. The techniques presented exploit the context available in a complex instruction and retain this information for use in subsequent execution of that instruction. Since this context is available only within a single instruction, low level instruction sets cannot benefit from this technique. In this sense the reduced instruction set machines as implemented in RISC are at their architectural limits, while complex instruction sets such as the VAX are far from theirs. For these reasons, complex instruction sets can have a significantly greater performance potential than a RISC instruction set for a given technology.

Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.

This study is concerned with measurements of the characteristics of current use of digital computer instruction sets, and an analysis of those measurements to produce conclusions useful for future design evaluation. The results include conclusions about computer architectures and their implementations. In order to apportion the time spent by an executing program among the various system components, a model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs, and the results are verified by comparison with actual performance. Measurements are made and discussed for other instruction set architectures, including a current microprocessor (the INTEL 8080), a popular minicomputer (the DEC PDP11), and a pseudo-computer used as an intermediate step for PASCAL compilation or interpretation. Some predictive models are investigated. An improved mechanism for conditional branch prediction is proposed and simulated. The performance of a radically different implementation of the 370 is examined and its performance is predicted. Finally, some of the data gathered is used as the basis for a model of the instruction fetch process; that model is solved analytically. Design rules which should be followed to allow instruction sets to be implemented with high-performance processors are given. 27 figures, 24 tables.

Computer architecture classes do not provide students with laboratory experience in the design of instruction set architectures. Projects that compare designs have not been possible due to a lack of support software. The design and evaluation of a new instruction set requires an assembler, a symbolic debugger, and a statistics gatherer. Every new instruction set requires changes to all three programs. It would be unrealistic to expect that either students or instructor would (re)write such software in order to evaluate each new design.A new, flexible software package called the Instruction Set Testbed (IST) provides for the comparison of instruction set architectures without writing any of the support software. IST's table-driven assembler uses a student-supplied architecture definition to assemble programs. IST's interactive debugger and a statistics gatherer also have access to the architecture definition. This allows symbolic debugging of the assembly language programs and automatic histogramming of instruction usage in the student-defined architecture.IST has been used in both undergraduate and graduate architecture classes to investigate such topics as orthogonality, choice and number of operands, addressing modes, and RISC philosophy.

Code execution in modern superscalar processors is inherently redundant. Many instructions execute repeatedly with the same inputs, producing the same outputs, thus wasting resources in the process. Value reuse techniques memorize previous executions of instructions, blocks or traces which may be reused if they appear again with the same input contexts. Although trace reuse techniques show great potential for both performance and energy consumption improvement, they have not been studied yet in one of the most widely available computer architectures - the ARM architecture. In this paper, the main issues with reusing traces in instruction sets with conditional execution are revisited. Afterwards, the reuse potential in the benchmark suite MiBench is analyzed varying (i) how traces are generated, and (ii) the size of reuse tables. Our results show that a memoization table of 32 KiB allows to reuse 18.36% of the total instructions on average.

This paper describes a novel video specific instruction set architecture for ASIP design. With SIMD (Single Instruction Multiple Data) instructions, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS ISA (Video Specific Instruction Set Architecture), other DSPs (digital signal processors) and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS ISA improves the processors performance by approximate 5x on H.263 encoding, and VS ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

Computer architectures sit at an important juncture between ever-changing landscape of implementation technology and emerging applications.It presented with a crucial connect between the plane of abstract algorithm and detailed computing and storage technologies -through the lens of Instruction-Set Architectures (ISA) and micro-architecture.Over the years, the architectures evolved to cater to various applications, with the core objective of achieving better runtime, smaller area, and lesser power consumption.This led to pathbreaking innovations, which, in turn catapulted various application segments to prominence, such as wireless/mobile computing, graphics processing, and more recently machine learning.It is a difficult task to capture such momentum with various tributaries in a single volume and yet, this is what is attempted in the current Handbook of Computer Architectures.While the content follows a standard narrative, the format of this book is unique.It offers live update of the content, thereby allowing the authors to include modern developments within the same context of a specific topic.The content is spread over multiple sections, and in each section, specific chapters offer a detailed glimpse of a topic of interest.The chapters are presented in increasing order of advanced concepts.It is also cross-linked in such a manner that reader can peruse a chapter with only necessary pre-requisite from selected, prior chapters.In the first section of single-core processors, three chapters provide the background of computer organization, microarchitecture, and communication networks.This is complemented with chapters on operating systems, edge computing, and secure computing architectures -which provide sufficient foundation for a reader to move toward more advanced notions in any of the following sections.The section on application-specific processors provides valuable insights into the growing demands from application developers to have customized architectures, also referred to as co-processors or accelerators.From a wide range of application segments, multimedia processing, scientific computing, machine learning, and cryptographic workloads are chosen to be covered here.Since these applications heavily depend on digital arithmetic, a short overview of the concepts is presented as well.Multimedia, machine learning, and several other domain-specific architectures are known to get influenced -for good or worse -due to the device-level faults appearing in advanced technology nodes.This is discussed in the section of faulttolerant architectures.

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.

Control-flow computer architectures are based on the von Neumann paradigm. They are flexible enough to support the execution of instructions in any order. Each instruction is fetched from the memory before it could be executed. Passing the data from the instruction that produces it to the instruction that requires it is done using registers or memory. DataFlow computer architectures are configured for execution of an algorithm, while data travel through the hardware. They are suitable for high-performance computing, where the same set of instructions should be run many times. Initialization of data and other processing is done by the processor based on control-flow. The Maxeler framework provides functionality for transforming any algorithm into a VHDL file, and further configuring the dataflow hardware. It also provides support for sending data from the control-flow host processor to the dataflow hardware, and bringing results back. Common programming languages are supported for the host processor, while dataflow hardware programming is done in MaxJ, which is an extended subset of the Java programming language. One can use an integrated development environment called MaxIDE, which is based on Eclipse. We present here a perspective overview of a cloud-supported web-based integrated development environment, WebIDE, which is a subset of MaxIDE, and enables users to develop and run programs for dataflow hardware even without owning dataflow hardware. The main concepts are explained, as well as differences in two integrated development environments. Then, our main focus is on the point of view of programmers, and the goal is to compare the MaxIDE and the WebIDE Maxeler framework, describing the technology needed to support the WebIDE Maxeler framework, providing that the MaxIDE already exists.

We present an algorithm for compiler-driven register name adjustment with the main goal of power minimization on instruction fetch and register file access. In most instruction set architecture (ISA) designs, the register fields reside in fixed positions within the instruction encoding, hence forming streams of indices on the instruction bus and to the register file address decoder. The number of bit transitions in these streams greatly determines the power consumption on the address bus and the register file decoder. While general-purpose registers are semantically indistinguishable and hence interchangeable, the particular register indices do have a direct impact on power consumption. The algorithms presented in this paper address this power minimization problem by reassigning/encoding the registers so that the bit transitions within the register index streams are minimized.