On Cloud-Supported Web-Based Integrated Development Environment for Programming DataFlow Architectures

Many Integrated Development Environment (IDE) can be used to create Android Apps. Android Studio with Java programming language is an IDE and native programming language that is officially supported by Google. As a supported IDE, AS becomes the best IDE that can be used to build apps. Nevertheless, many novice programmers find it difficult to get started especially by starting a new programming concept for mobile devices. Android Studio is also known as an IDE that requires a high specs computer requirement and also has sophisticated features. This research purposed to develop applications with IDEs that are more user-friendly and more emphasize the big concept of programming without much difficulty regarding compiling the program code and also the complexity of IDE as well as Android Studio. The IDE used in this study is App Inventor 2 (AI2), a cloud-based IDE managed by the Massachusetts Institute of Technology (MIT). The next goal is to test the capabilities of the application by conducting Blackbox Testing and User Testing. In this research has been developed an app called Receptionist that is used to test the ability of the codes generated by AI2. The results show that AI2 can be used to build complex applications such as Text Message Service (SMS) broadcasting, performing local database queries and retrieving data on the server. However, some features such as database processing should run in the background still run on the UI thread, thereby reducing the user experience when Application Not Responding (ANR) occurs. Keywords: App Inventor 2, Android Application, Cloud Programming, visual programming

The article is devoted to the analysis of the analysis of the experience of teaching the most common modern programming languages in the leading institutions of higher education in Ukraine. The purpose of the article is to analyze the experience of teaching the most common modern programming languages in leading Ukrainian higher education institutions in order to determine the relevance of knowledge provided by the leading institutions of higher education of Ukraine regarding the modern popularity of programming languages. Based on recent research and publications and work plans of leading institutions of higher education, the necessary information was gathered and an analysis of the experience of training the most common modern programming languages was conducted.

Software is rapidly moving from the desktop to the Web. The Web provides a generic user interface that allows ubiquitous access, instant collaboration, integration with other online services, and avoids installation and configuration on desktop computers. For software development, the Web presents a shift away from developer workstations as a silo, and has the promise of closer collaboration and improved feedback through innovations in Web-based interactive development environments (IDEs). Moving IDEs to the Web is not just a matter of porting desktop IDEs; a fundamental reconsideration of the IDE architecture is necessary in order to realize the full potential that the combination of modern IDEs and the Web can offer. This paper discusses research challenges and opportunities in this area, guided by a pilot study of a web IDE implementation.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

Chapter Two - Emulation: Interpretation and Binary Translation

The data acquisition facility for the LEGS medium energy photonuclear beam line is composed of an auxiliary crate controller (ACC) acting as a front-end processor, loosely coupled to a time-sharing host computer based on a UNIX-like enviromnent. The ACC services all real-time demands in the CAMAC crate: it responds to LAMs generated by data acquisition modules, to keyboard commands, and it refreshes the graphics display at frequent intervals. The host processor is needed only for printing histograms and recording event buffers on magnetic tape. The host also provides the environment for software development. The CAMAC crate is interfaced by a VERSAbus CAMAC branch driver.

Recent advances in different instruction set architectures (ISAs) and their implementations have revived the argument on the role of ISAs in the overall performance and energy efficiency of a processor. Many computer architects believe that with current compiler and microarchitecture developments, the choice of ISA is not a decisive matter anymore. On the other hand, some believe that ISAs can still play an important role in the overall performance and energy efficiency of a computer system. Our objective is to compare and contrast ISAs by finding the differences in performance and energy consumption across ISAs and the reasons behind those differences. Our work shows that ISAs affect the performance and energy efficiency of applications differently based on their inherent characteristics.

Matthias Felleisen was awarded the 2011 SIGCSE Award for Outstanding Contribution to Computer Science Education for his and his research team's work on the TeachScheme! project, which was begun in 1995, and is now called by Design. This functions-first approach to teaching introductory programming and problem-solving features a robust software design methodology called the design recipe, and emphasizes good software engineering practices, such as early testing, from the beginning. These are combined with an integrated development environment (IDE), DrRacket, designed for beginners, featuring different language levels of the Scheme-like language, Racket, that combines simple syntax with customized error messages and support for graphics and animation accessible even for beginning programmers. The Program by Design project then includes support for transitioning to object-oriented programming in Java. However, many of this approach's concepts can be applied in different programming languages (such as Java, Python, or C++), or one can choose to start with this approach and then transition to different programming paradigms and/or languages at a pace appropriate to your situation.

Model checking is a technique for finding bugs in systems by systematically exploring their state spaces. We wish to extract sound models from concurrent programs automatically and check the behaviors of these models systematically. The zing project is an effort to build a flexible infrastructure to represent and model check abstractions of large concurrent software.To support automatic extraction of models from programs written in common programming languages, zing’s modeling language supports three facilities present in modern programming languages: (1) procedure calls with a call-stack, (2) objects with dynamic allocation, and (3) processes with dynamic creation, using both shared memory and message passing for communication. We believe that these three facilities capture the essence of model checking modern concurrent software.Building a scalable model-checker for such an expressive modeling language is a huge challenge. zing’s modular architecture provides a clear separation between the expressive semantics of the modeling language, and a simple view of zing programs as labeled transition systems. This separation has allowed us to decouple the design of efficient model checking algorithms from the complexity of supporting rich constructs in the modeling language. zing’s model checking algorithms have been designed to exploit existing structural abstractions in concurrent programs such as processes and procedure calls. We present two such novel techniques in the paper: (1) compositional checking of zing models for message-passing programs using a conformance theory inspired by work in the process algebra community, and (2) a new summarization algorithm, which enables zing to reuse work at procedure boundaries by extending interprocedural data-flow analysis algorithms from the compiler community to analyze concurrent programs.KeywordsModel CheckModeling LanguageProcedure CallLabel Transition SystemConcurrent ProgramThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This book – the first of two volumes – explores the syntactical constructs of the most common programming languages, and sheds a mathematical light on their semantics, while also providing an accurate presentation of the material aspects that interfere with coding. Concepts and Semantics of Programming Languages 1 is dedicated to functional and imperative features. Included is the formal study of the semantics of typing and execution; their acquisition is facilitated by implementation into OCaml and Python, as well as by worked examples. Data representation is considered in detail: endianness, pointers, memory management, union types and pattern-matching, etc., with examples in OCaml, C and C++. The second volume introduces a specific model for studying modular and object features and uses this model to present Ada and OCaml modules, and subsequently Java, C++, OCaml and Python classes and objects. This book is intended not only for computer science students and teachers but also seasoned programmers, who will find a guide to reading reference manuals and the foundations of program verification.

This paper presents a collaborative software development platform allowing traditional and virtual universities actors who are geographically distant to work on a software development project using common (usual) programming languages. In the context of the virtual universities operating in the field of STEM (Science, Technology, Engineering and Mathematics), pratical classes are needed to acquire and to enhance the necessary skills particularly in software engineering. To the various actors of these digital and traditional universities making some e-learning, this paper supplies a preconfigured collaborative software development environment including synchronization of files belonging to a given project, instant messaging, audio and video. Our platform has an administration interface allowing the management of permissions and preconfigured virtual machines allocation to the various actors. To reach our goals, we used the XMPP protocol for instant messaging and file synchronization. Then, we used WebRTC for audio and video between actors. Finally, we used the RDP protocol to allow the access to the virtual machines. In this work, we show how our platform was used by the Virtual University of the Senegal (UVS) teachers and students in the field of Applied Mathematics and Computer Science for some pratical classes about C/C++, Java, Python and PHP programming languages.

Debugging is an important aspect of programming. Most programming languages have some features and tools to facilitate debugging. As the debugging process is also frustrating, it requires good scaffolding, in which a debugger can be a useful tool [3]. Scratch is a visual block-based programming language that is commonly used to teach programming to children, aged 10--14 [4]. It comes with its own integrated development environment (IDE), where children can edit and run their code. This IDE misses some of the tools that are available in traditional IDEs, such as a debugger. In response to this challenge, we developed Blink. Blink is a debugger for Scratch with the aim of being usable to the young audience that typically uses Scratch.

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

: This exploratory development program was originally aimed at developing a computer with features to specifically support the JOVIAL (J73) programming language with considerations to Ada. Later, the program was redirected to modify the instruction set architecture (ISA) to more fully support Ada and increase performance. The new ISA supports most of the standard functions found in most ISA, but gives additional supports in: the Ada package concept, processing arrays nd records, unconstrained arrays, dynamic storage allocation, detecting dangling references, detecting undefined variables, Ada-like exception handling, case instructions, for-loop instructions, Ada-like parameter passing, Ada-like tasking instructions and IEEE-standard floating point data types. Keywords: High level language Ada machine, Semantic gap reduction; Language-directed architecture; Non-Von Neumann architecture; Object oriented architecture; Capability based addressing.